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Artificial Intelligence (AI) has exploded into mainstream consciousness with commercial investments exceeding $90 billion in the last year alone. Inasmuch as consumer-facing applications such ChatGPT offer astounding access to algorithms that were hitherto restricted to academic research labs, public focus of attention on AI has created an avalanche of misinformation. The nexus of investor-driven hype, “surprising” inaccuracies in the answers provided by AI models – now anthropomorphically labeled as “hallucinations”, and impending legislation by well-meaning and concerned governments has resulted in a crisis of confidence in the science of AI. The primary driver for AI’s recent growth is the convergence of ubiquitous cloud computing technology and pivotal developments in artificial neural network (ANN) architectures and machine learning topologies, leading to the emergence and dominance of large language models. These models have cast aside the need for extensive data pre-processing and incorporate feature extraction into network training. In some cases, such as in the use of generative AI models for natural language processing, the results are astonishing, but also, in many ways, concerning. An overreliance on the network to perform multiple tasks, well beyond data interpolation, leads to output anomalies and errors. Also, increasing the size of datasets and number of network layers to ensure better performance is soon to hit a brick wall of incurred time and expense to train the network. But of greatest concern, despite the race to advance the technology, is that we are unable to adequately describe the operation of AI models mathematically, and, therefore, we do not completely understand how such systems develop the relationships within the training data to produce results. It is in this context that the research work presented in this dissertation comprehensively investigates the origins of ANNs based on approximation theory, in order to refocus efforts on data pre-processing, and away from the exclusive attention on the development of more and more complex architectures. In a sense, the science and mathematics of AI algorithms must provide a path for the robust, reliable, and rapid deployment of intelligent algorithms without an over-reliance of technological prowess – inexpensive bandwidth and computing power. An algorithm for shape recognition in image data is developed based on geometric transformations, which forms the input to data to any neural network architecture of choice. Results demonstrate that such intelligent pre-processing provides significantly more control to the network designer than brute-force methods of exponentially increasing network layers.

As technology advances, the field of electrical and computer engineering continuously demands innovative tools and methodologies to facilitate effective learning and comprehension of fundamental concepts. Through a comprehensive literature review, it was discovered that there was a gap in the current research on using VR technology to effectively visualize and comprehend non-observable electrical characteristics of electronic circuits. This thesis explores the integration of Virtual Reality (VR) technology and real-time electronic circuit simulation with enhanced visualization of non-observable concepts such as voltage distribution and current flow within these circuits. The primary objective is to develop an immersive educational platform that makes understanding these abstract concepts intuitive and engaging. This research thesis implements the design and development of a VR-based circuit simulation environment. By leveraging VR’s immersive capabilities, users can physically interact with electronic components, observe the flow of electrical signals, and manipulate circuit parameters in real-time. Through this immersive experience, learners can gain a deeper understanding of different fundamental electronic principles, transcending the limitations of traditional two-dimensional diagrams and equations. Furthermore, this thesis focuses on the research and implementation of advanced and novel visualization techniques within the VR environment for non-observable electrical and electromagnetic properties to provide users with a clearer and more intuitive understanding of electrical circuit concepts. Examples include color-coded pathways for current flow and dynamic voltage gradient visualization. Additionally, real-time data representation and graphical overlays are researched and integrated to offer users insights into the dynamic behavior of circuits, allowing for better analysis and troubleshooting. Advisor: Hamid R. Sharif-Kashani

Silicon Carbide (SiC) Field-Effect Transistor (FET) modules lead the way in power electronics, being superior in efficiency and robustness for high-frequency applications. The shift towards SiC from traditional silicon (Si)-based devices is driven by its superior thermal conductivity, higher electric field strength, and operational efficiency at elevated temperatures. These features are critical for the development of next-generation, grid-oriented power converters aimed at enhancing the reliability and sustainability of power systems. This research focuses on high-frequency press-pack (HFPP) SiC FET modules, addressing the primary challenge of miniaturizing SiC FET dies without compromising performance, through an innovative press-contact design essential for increased high-frequency efficiency. The objective of the research is to develop and validate a novel monolithic spring (MS) for HFPP SiC FET modules, aiming to surpass conventional press-pack (PP) limitations. By machining airgap slits from a beryllium–copper block, the proposed MS design seeks to achieve optimal mechanical and electrical performance, targeting a linear spring constant, minimal stray inductance, and enhanced high-frequency body resistance. This approach combines theoretical modeling, finite element analysis (FEA) simulations, and experimental validation to overcome the inefficiencies of existing designs, thereby advancing HFPP SiC module technology and supporting the broader adoption of SiC FET in power systems. Additionally, FEA simulations are employed to contrast the novel MS design with traditional Si-based transistors, highlighting the MS's advanced performance and efficiency in high-frequency applications. The research signifies a vital step towards improving the performance and sustainability of electrical grids worldwide, demonstrating the potential of SiC technology in transforming power conversion systems. Advisors: Liyan Qu and Jun Wang

The information-containing nature of the DNA molecule has been long known and observed. One technique for quantifying the relationships existing within the information contained in DNA sequences is an entity from information theory known as the average mutual information (AMI) profile. This investigation sought to use principally the AMI profile along with a few other metrics to explore the structure of the information contained in DNA sequences. Treating DNA sequences as an information source, several computational methods were employed to model their information structure. Maximum likelihood and maximum a posteriori estimators were used to predict missing bases in DNA sequences. Other novel prediction methods based upon the AMI profile and its ability to evaluate the predictability of DNA bases were also developed and tested for accuracy. The AMI profile was also adjusted to account for the triplet-code nature of DNA sequences. Additionally, machine-learning techniques such as neural networks, support vector machines, and principal component analysis were used to classify different regions of DNA sequences using the AMI profile and to compare coding versus noncoding regions. Finally, the analysis considered the relative frequency of groups of bases (known as k-mers) in DNA sequences. Arithmetic coding was explored as a way to effect the compression of DNA sequences modeled upon the relative frequency of the appearance of k-mers. It was concluded that biological information stored in DNA is complex, yet this investigation provided methods to elucidate some of the character of the information structure of DNA sequences. Advisor: Khalid Sayood

Wind power is one of the world's fastest-growing renewable energy resources and has expanded quickly within the US electric grid. Currently, wind power producers (WPPs) may sell energy products in US markets but are not allowed to sell reserve products, due to the uncertain and intermittent nature of wind power. However, as wind’s share of the power supply grows, it may eventually be necessary for WPPs to contribute to system-wide reserves. This paper proposes a stochastic optimization model to determine the optimal offer strategy for a WPP that participates in the day-ahead and real-time energy and spinning reserve markets. The objective function maximizes the WPP’s total expected profit while minimizing risk by allowing the WPP to split its offers between the energy market and the spinning reserve market, which has lower penalties for failing to deliver the cleared day-ahead offer. Risk is considered through the Conditional Value at Risk metric and several risk aversion levels are studied. Case study results show that the proposed offer strategy increases expected profit and decreases risk compared to the case where the WPP only participates in the energy market. Advisors: Wei Qiao and Liyan Qu

Deep neural networks (DNNs) have achieved unprecedented success in many fields. However, robustness and trustworthiness have become emerging concerns since DNNs are vulnerable to various attacks and susceptible to data distributional shifts. Attacks such as data poisoning and out-of-distribution scenarios such as natural corruption significantly undermine the performance and robustness of DNNs in model training and inference and impose uncertainty and insecurity on the deployment in real-world applications. Thus, it is crucial to investigate threats and challenges against deep neural networks, develop corresponding countermeasures, and dig into design tactics to secure their safety and reliability. The works investigated in this dissertation constitute our pioneering efforts in robust and trustworthy deep learning from perspectives of attacks, defenses and designs.

This dissertation investigates efficient power system electromagnetic transient (EMT) simulations using a semi-analytical approach. First, based on state-space equations of system EMT models, a semi-analytical solution (SAS) is acquired using the Differential Transformation Method (DTM). The DTM can efficiently derive the SAS of any linear or nonlinear system as a power series in time in a recursive manner using well-developed transformation rules. A high-order SAS allows a large time step to speed up the simulation while maintaining the same level of accuracy. Also, a variable time step approach is proposed to further improve its efficiency. Case studies on multiple systems demonstrate that the proposed approach has better performance compared to traditional numerical approaches. Second, to effectively handle switches caused by limit violations during simulations, a binary search-enhanced quadratic-interpolation algorithm is proposed to precisely locate the transition moment and correct the simulation using the SAS. Case studies on a full EMT model of the IEEE 39-bus system are conducted to show the high accuracy of the proposed detection approach. Third, while the network is solved by a nodal equation instead of a state-space equation, the SAS is explored on synchronous generators and controllers. An interface between the two different numerical approaches is developed based on the extrapolation of terminal voltages. At the same accuracy, the SAS can still improve the simulation efficiency using a larger time step. Fourth, the parallel SAS-based EMT simulation using a nodal equation for the network is studied and tested. The network solution is parallelized through reformulating the network conductance matrix into a bordered block diagonal (BBD) form. The SAS-represented synchronous generators are naturally decoupled and parallelized. Case studies on a synthetic 10024-bus system demonstrate the high performance of the parallel simulation. Fifth, a high-order nodal approach for the network equation based on diagonally implicit Runge-Kutta methods is proposed and interfaced with the SAS of generator and controller equations. Case studies on a four-bus system show that the proposed approach has higher efficiency compared with the traditional approach.

Next-generation communications (Next-G), such as 6G, are expected to support emerging networked intelligent systems, including autonomous driving, factory automation, digital twin technology, unmanned aerial vehicle (UAV) navigation, and extended reality. Timely inference is crucial for these networked intelligent systems. In this dissertation, we investigate a remote inference system, where a trained neural network is used to infer time-varying targets (e.g., the locations of vehicles and pedestrians) based on features (e.g., video frames) observed at a sensing node (e.g., a camera). The inference error is determined by (i) the timeliness and (ii) the sequence length of the features, where we use the Age of Information (AoI) as a metric for timeliness. In the first part of the dissertation, we discuss how to evaluate the importance of timely information in remote inference and the monotonicity of information aging. One might expect that the performance of a remote inference system degrades monotonically as the feature becomes stale. Using a new information-theoretic analysis, we show that this is true if the feature and target data sequence can be closely approximated as a Markov chain; it is not true if the data sequence is far from Markovian. Hence, the inference error is a function of the AoI, where the function could be non-monotonic. In addition, a longer feature can typically provide better inference performance, but it often requires more channel resources for sending the feature. In the second part of the dissertation, we study the transmission scheduling problem that optimizes timeliness and feature sequence length to minimize inference error. We introduce a new "selection-from-buffer" medium access model for status updating and minimize inference errors for both Markovian and non-Markovian data. For single-source and single-channel remote inference networks, we obtain optimal scheduling policies for both the cases of time-invariant and time-variant feature lengths. In multi-sources and multi-channel remote inference networks, the selection-from-buffer scheduling problem is a multi-action restless multi-arm bandit problem. For this setting, we design new scheduling policies by utilizing the Whittle index and duality-based gain index. The new scheduling policies are proven to be asymptotically optimal. Data-driven evaluations show that our policies can reduce inference errors by up to 10,000 times.

In real-time monitoring and networked control systems, sensor observations from vehicles, robots, UAVs, or stock markets, are transmitted to a monitoring or controlling unit, which could be any kind of decision-making device. Real-time services often require fresh and timely data which are usually in the form of a signal. A key performance metric characterizing data freshness is the Age of Information (AoI). However, data signals can exhibit diverse behavior, sometimes evolving slowly and later on evolving very quickly. Therefore, only considering the time difference is insufficient to characterize the variation of a signal. In this dissertation, we investigate the performance of a remote estimation system by considering both the data signal value and its timeliness. First, we consider the sampling problem for the remote estimation of a scalar Gauss-Markov process. The optimal sampling problem is a constrained continuous-time Markov Decision Process (MDP) with an uncountable state space. Our analysis reveals that the optimal sampling policy is a threshold policy on instantaneous estimation error and the threshold is found. If the sampler has no knowledge of the process, the optimal sampling problem reduces to an MDP for minimizing nonlinear age functions. In both problems, the optimal sampling policies can be computed by low-complexity algorithms. Next, We generalize this study from single-source, single-channel to multiple-source, multiple-channel and formulate a scheduling problem for the remote estimation of multiple Gauss-Markov processes. This problem is a continuous-time Restless Multi-armed Bandit (RMAB) with a continuous state space. We prove that all bandits are indexable and derive an exact expression of the Whittle index. Our results unite two theoretical frameworks that are used for remote estimation and AoI minimization: threshold-based sampling and Whittle index-based scheduling. In these investigations, the numerical evidence shows that our proposed policy achieves high-performance gain over existing policies. Finally, we study a scheduling problem for maximizing situational awareness in safety-critical systems where a centralized monitor pulls updates from multiple agents monitoring several safety-critical situations. Based on the received updates, multiple estimators determine the current safety-critical situations. We provide a novel framework that quantifies the loss due to the unawareness of potential danger which depends on the AoI and the observed signal value. To minimize the penalty, we study an RMAB problem and provide a low-complexity scheduling algorithm that is asymptotically optimal. Numerical evidence shows that our scheduling policy can achieve up to 100 times performance gain over periodic updating and up to 10 times over randomized policy.

This work investigates the RF characterization and modeling of noise, linearity, and reliability of advanced RF FinFETs. 5-nm technology devices are used in linearity and noise modeling, and 14-nm technology devices are used for reliability and noise γ factor. The impact of non-conducting RF and DC stresses on IO devices in a 14/16-nm production FinFET technology is investigated experimentally. Degradation of transistor I − V and key RF characteristics are examined. At Vgs=0 V, the DC, and RF stress degradations show very different time exponents (n), making quasi-static approximation impossible. RF NC stress produces more long-term transistor performance degradation than its DC NC stress counterpart for the same maximum drain voltage. Despite RF stress, it has a smaller degradation at short stress times. All the RF stress degradation share a common n and exhibit a Vds,max dependence that can be modeled using Takeda’s equation. At Vgs=0.5 V, a significant die-to-die degradation variation is observed for near-threshold stress, which we attribute to subthreshold current variations. By modeling the die-to-die variation of the source current, we show that the RF stress degradation is reasonably quasi-static. The result supports channel current as the pri mary source of hot carriers, as is in conducting stress [1], despite the much lower Vgs. A simple method for a quick inspection of the impact of die-to-die variation is demonstrated. In both cases, the modeled Vds,max is found to be sufficient for our intended PAs. RF measurements of Cgs, Cgd, gm, and gds suggest that the damages are located near the drain end of the channel within the pinch-off region in saturation. The two-tone intermodulation linearity characteristics are investigated using RF measurement, circuit simulation with BSIM-CMG, and power series IP3 analysis. For a given VDS, there are two IP3 peaks with respect to VGS. The VGS of the second IP3 peak corresponds to the VGS for which the Vdsat is equal to the VDS when the VGS is used for VDS sweep. Key BSIM-CMG model parameters required for simultaneous fitting of DC I-V, S-parameters, and intermodulation distortion are provided, in which parameters for the DIBL effect are most important for distortion. Power series is used in device linearity analysis, and power series calculated IP3 well agrees with measurement and simulation. Eliminating extra self-heating on IP3 coefficients and correcting derivatives from large parasitics are key steps to obtain accurate IP3 in the power series method. Detailed power series IP3 analysis shows that A, B, and C cancel out, causing a peak of IIP3 for sweeping VDS. The IP3 is strongly affected by load resistance RL. It is also observed that the load resistance, RL, significantly influences the IP3.

Modern cryptography and the digital world (CMOS mainly) have been advancing side-by-side. Although cryptographic algorithms only need to be proven with theoretical soundness, cryptographic engineering on digital device requires more efforts to achieve a secure implementation than simply just design theories. Although properties like energy-efficiency, low-latency, and minimal area overhead are desired in hardware-based implementations for cryptographic modules, they could potentially weaken the theoretical justification of cryptosystems, where adversaries can break the secret key inside the hardware. In this dissertation, we develop novel attack to uniquely determine the secret key for hardware implementation of GIFT-COFB, one of the ten finalists for National Institute of Standards and Technology (NIST) Lightweight Cryptography Standardization Process. The 2-round partial unrolled design of GIFT-COFB is shown to be the most energy-efficient among all other $r$-round partial unrolling and fully unrolled settings. Our proposed chosen-plaintext attack can effectively break the master key $K$ on this 2-round partial unrolled GIFT-COFB. In addition, we present two chosen-plaintext attacks on multicycle AES implementations with fault-based attacks. Both attacks on GIFT-COFB and multicycle AES include explanations from algebraic cryptanalysis perspective. In parallel, the adoption of horizontal business models in semiconductor manufacturing is negatively affected by the overproduction of integrated circuits (ICs) and the piracy of intellectual properties (IPs), which compromised the integrity of the digital world's semiconductor supply chain. Logic locking emerges as a primary design-for-security measure to counter these threats, where ICs become fully functional only when unlocked with a secret key. However, Boolean satisfiability-based attacks have rendered most locking schemes ineffective. This gives rise to numerous defenses and new locking methods to achieve SAT resiliency. Subsequent attacks have been proposed to target these newly proposed solutions. The reasons behind the effectiveness of SAT attack and the following SAT-based attack have yet to be explored. In this dissertation, we provide a unique perspective on SAT attack efficiency based on conjunctive normal form (CNF) stored in SAT solver. We demonstrate how this attack learns new relations between keys in every iteration using distinguishing input patterns and the corresponding oracle responses. Each input-output pair gives additional CNF clauses of unknown keys to be appended to SAT formulation, which leads to an exponential reduction in incorrect key values. Overall, SAT attack is shown to break most locking scheme within the linear iteration complexity of key size. Our analysis provides a new perspective on the capabilities of SAT attack against multiplier benchmark c6288 with possibly new directions to achieve SAT resiliency. In the digital world, it is also crucial to reduce manufacturing defect escapes in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zero-defect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100\% fault coverage. It remains challenging to detect hard-to-detect and redundant faults for large VLSI circuits. More optimization needs to be done as undetected faults still exist under the state-of-the-art commercial ATPG tools. Rather than attacking logic locking with SAT solvers, in this dissertation, we propose a novel test pattern generation approach constructively using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the key is a test for the stuck-at fault. We propose two different approaches for test pattern generation. First, a single stuck-at fault is targeted, and a corresponding locked circuit with one key bit is created. This approach generated one test pattern per fault. We also consider a group of faults and convert the circuit to its locked version with multiple key bits. The inputs obtained from the SAT attack tool are the test set for detecting this group of faults. Our approach finds test patterns for all hard-to-detect faults that were previously undetected in commercial ATPG tools. The proposed test pattern generation approach can efficiently detect redundant faults with ITC'99 benchmarks. The results show that we can detect all the hard-to-detect faults and identify redundant faults, and a 100\% stuck fault coverage is achieved. Finally, we consider privacy-enhancing solutions to offer additional benefits for securing the digital world. In this dissertation, we develop an efficient, secure, and on-demand communication protocol using zero-knowledge proofs (ZKPs) that allow the prover to provide evidence of its secret without revealing that to the verifier. The edge device, acting as the prover, convinces the central server, the verifier, of the unique PUF response stored inside the device without requiring the actual storage of PUF responses on the server. The non-interactive characteristic of zk-SNARK, Zero-Knowledge Succinct Non-Interactive Argument of Knowledge, offers better optimization to authentication frequency, communication bandwidth between device and server, and protection of device-specific secret, all of which contribute to constructing our proposed device authentication framework.

The perpetual need for faster data rates continues to drive advancements in wired and wireless communication, pushing them toward higher operating frequencies. The upcoming 5G network demands mobile transceivers that can function across an extensive frequency spectrum, spanning from sub-6GHz to millimeter-wave frequencies. This presents fresh, significant challenges in designing integrated frequency synthesis circuits that achieve both low jitter and low power consumption. This dissertation highlights the author’s research endeavors encompassing three key areas: (1) An injection-locked mm-wave frequency multiplier equipped with a low-power auxiliary frequency tracking loop for robust locking. (2) Injection-locked frequency dividers offering wide-range integer and fractional division ratios. (3) The utilization of these components in a 40GHz mm-wave frequency synthesizer to achieve low noise and low power consumption. The frequency multiplier employs a 40GHz injection-locked oscillator (ILO) for 4x frequency multiplication. It incorporates a low-power digital frequency tracking loop (FTL) to detect actual frequency errors, enabling a wide operating range for the ILO while employing a high-Q tank for reduced power consumption. The frequency dividers leverage injection-locked dynamic latches to achieve low-power integer and fractional multi-modulus at mm-wave bands. Programmable divide ratios are achieved by adjusting stage delays using variable PMOS load resistance and varactor capacitance. Circuit analysis shows that by incorporating proper phase delays, the fundamental frequency mixing provides integer frequency division, while the second harmonic mixing enables fractional frequency division. The prototype divider operates within an input frequency band of 27-44GHz, offering division ratios programmable as 4, 4.5, 5, 5.5, and 6. Implemented in a 45nm PDSOI CMOS technology, it consumes a maximum power of 2.4mW at a 0.94V supply voltage, occupying a compact core area of only 1368μm2. Both the frequency multiplier and divider contribute to a two-stage mm-wave frequency synthesizer. This two-stage approach allows for separate handling of low phase noise frequency synthesis via a slope-reshaped Reference Sampling Phase-Locked Loop in the first stage and mm-wave frequency multiplication in the second stage, optimizing overall power efficiency. Fabricated using a 45nm PDSOI CMOS technology, the prototype synthesizer achieves 251fs integrated jitter with a power consumption of 20.6mW at 35.84GHz, achieving a Figure of Merit (FoM) of -238.9dB, and occupying a mere 0.41mm2. These achievements have been published in IEEE Custom Integrated Circuits Conference and IEEE Journal of Solid-State Circuits. In a short period of time, the publications have received impactful citations in leading journals and conferences.

Permanent magnet synchronous motors (PMSMs) are widely used due to their simple structure, high performance, and simple control strategies. Over the years, several control techniques have been developed in motor control, whereas vector control, which is also called field-oriented control (FOC), has had great success in PMSM control. The concept of FOC is that the motor torque and flux are decoupled from each other, which means they can be controlled separately. Since torque control is achieved by the speed controller, it can be considered that the speed and the flux of the PMSM are also decoupled from each other and can be controlled separately. As a result, vector control of a three-phase PMSM using decoupled flux and speed control is proposed in this work. The FOC scheme is used, and separate flux and speed regulators are proposed. In addition, two control methods are applied. The first method is based on the proportional-integral (PI) controller, while the second method is based on the proportional-resonant (PR) controller. As a result, decoupled speed and flux control of three-phase PMSM based on the PI control method and decoupled speed and flux control of three-phase PMSM based on the PR control method are proposed. In addition, a comparative study of PMSM torque control using PI and PR control methods is undertaken. The study compares the motor performance of the PMSM based on each method and the complexity of the overall control scheme. Also, the behavior of the PMSM is studied under the open circuit fault condition. Hence, vector control of PMSM based on a PR controller under an open-circuit fault is studied. During the fault situation, it is challenging to guarantee the continuous operation of the motor, achieve good steady-state and dynamic performance, and reduce the ripple in the speed and flux response. However, the PR control method proves its efficacy in controlling the PMSM under OCF conditions.

Microgrids are localized, independent power grids that can operate while connected to the larger electrical grid. These systems make intelligent decisions regarding power management and use an array of components to monitor power generation, consumption, and environmental conditions. While this technology can save end users money, the complexity of installation and maintenance has limited the adoption of microgrids in residential spaces. To simplify this technology for end users, the next evolution of microgrid components includes sensors that are wireless and ambiently powered. Even with a microgrid installed, significant energy is wasted in residential spaces. To address this loss, energy harvesting circuits can be incorporated into microgrid sensors, enabling them to recapture otherwise wasted environmental energy. Light, heat, radio frequency (RF) energy, mechanical energy, and 60 Hz noise from power lines are all abundant in most residential spaces and can be harvested to power microgrid components. Equipping microgrid sensors with energy harvesters simplifies the end user experience by eliminating the need for cable routing. Implementing energy harvesting techniques results in a microgrid that is easier to deploy, cleaner, and requires less maintenance. Developing this type of sensor is not only feasible, but sensible and can be constructed using off-the-shelf components. My research led me to conclude that the most effective strategy for designing an energy harvesting sensor is to combine energy harvesting technologies with battery power. By delegating smaller loads away from the harvesting integrated circuit (IC), its full harvesting potential is utilized, maximizing energy collection for the power-hungry transmitter. Simultaneously, a small coin-cell battery can sustain the remaining components, ensuring over a decade of functionality. This thesis explores the feasibility and design of a hybrid battery and energy harvesting sensor. The developed system block diagram allows for the swapping of components within each block, catering to the varying needs of the end user. The system is data and energy-aware, allowing it to make intelligent decisions regarding data transmission and enable communication as reliable as that of a traditional wire-line powered sensor. The hybrid sensor module underwent testing with a small monocrystalline solar cell as its energy source, delivering consistent power throughout the testing period. It accumulated surplus energy in a super capacitor storage unit, ensuring the system’s reliable operation even at night when the energy source was not available. While the tests utilized a photovoltaic (PV) cell, the design accommodates any energy harvesting source that can generate a minimum of 40 µW of power.

The primary goal of this dissertation is to investigate and improve the efficiency of deep learning algorithms, especially within computer vision problem domains, from the perspective of label-efficiency. This investigation showed that deep learning algorithms are mostly notorious for the lack of uncertainty representation. Accordingly, we aimed to develop an array of deep learning frameworks rich with uncertainty representation. These frameworks are mainly within two current pillars of machine learning, deep active learning and self-supervised learning. These frameworks include deep active ensemble sampling for efficient sample selection within deep active learning, a two-stage ensemble-based general self-training approach for existing visual self-supervised learning baselines, introduction of partial information decomposition to self-supervised learning and developing two techniques to exploit synergistic and unique information component within PID context, and a coloring approach for enhanced feature decoupling within self-supervised feature learning. Along with this major line of work, we also investigated the application of computational methods (e.g., machine learning and signal processing algorithms) in some problems in computational biology. This included applications in human genome sequence modeling, age estimation using gene expression data, age-related gene selection, and causal inference and association for age-related genes. Taken all these together, this dissertation shed insight on label-efficiency in deep learning, the efficient use of scarce data and resources (such as the case with computational biology), and on recent directions in generative AI.