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This brief proposes a low voltage ultra-low power 10-bit 100-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To overcome the performance degradation due to the signal-related current fluctuation under lower supply voltage, an adaptive-biasing comparator with current self-compensation (CSC) technique is proposed to obtain a constant working current, reducing the minimum supply voltage from 0.7V in conventional ADCs to 0.55V. Since full-scale range shrinks with the supply voltage, voltage undershoot in power rail caused by capacitor digital-to-analog converter (C-DAC) deteriorates effective-number-of-bits (ENOB). Conventional solutions involve enhanced regulators and large decoupling capacitors, which cost remarkable power dissipation and large chip area. This brief presents a pulse-injection undershoot compensation technique which reduces the DAC-related supply fluctuation from a typical 15mV to 1.8mV, and improves the ENOB by 0.4 bit. The prototype was fabricated in TSMC 28nm HPC CMOS technology. The proposed SAR ADC achieves an SNDR of 54.7dB and an SFDR of 68dB with the power consumption of 0.16mW under 0.55V supply voltage, a figure of merit (FoM) of 3.6-fJ/conversion-step is achieved. The chip area of the ADC core is 130μm×225μm.

This article demonstrates the potential of deep-subthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm² and consumes 15.9 μ W, resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

Photonics-based neural networks promise to outperform electronic counterparts, accelerating neural network computations while reducing power consumption and footprint. However, these solutions suffer from physical layer constraints arising from the underlying analog photonic hardware, impacting the resolution of computations (in terms of effective number of bits), requiring the use of positive-valued inputs, and imposing limitations in the fan-in and in the size of convolutional kernels. To abstract these constraints, in this paper we introduce the concept of Photonic-Aware Neural Network (PANN) architectures, i.e., deep neural network models aware of the photonic hardware constraints. Then, we devise PANN training schemes resorting to quantization strategies aimed to obtain the required neural network parameters in the fixed-point domain, compliant with the limited resolution of the underlying hardware. We finally carry out extensive simulations exploiting PANNs in image classification tasks on well-known datasets (MNIST, Fashion-MNIST, and Cifar-10) with varying bitwidths (i.e., 2, 4, and 6 bits). We consider two kernel sizes and two pooling schemes for each PANN model, exploiting $$2\times 2$$ 2 × 2 and $$3\times 3$$ 3 × 3 convolutional kernels, and max and average pooling, the latter more amenable to an optical implementation. $$3\times 3$$ 3 × 3 kernels perform better than $$2\times 2$$ 2 × 2 counterparts, while max and average pooling provide comparable results, with the latter performing better on MNIST and Cifar-10. The accuracy degradation due to the photonic hardware constraints is quite limited, especially on MNIST and Fashion-MNIST, demonstrating the feasibility of PANN approaches on computer vision tasks.

Resistive crossbar array for in-memory computing suffers from high static power and sneak-path current. To address these issues, we proposed a ferroelectric HfxZr1-xO2 (HZO) based capacitive crossbar array for in-memory computing. The non-volatile capacitive synapse allows the minimization of both sneak-path current and steady-state power consumption. Furthermore, since the capacitive synapse is read at DC 0V, we claim that this architecture allows read-disturbance-free and energy-efficient in-memory computing. In this paper, we first introduce the device properties of the non-volatile capacitor and their underlying physical mechanism. Moving to array-level analysis, we obtain the optimal ratios between reference and ferroelectric capacitors (Cref/CFE) for the maximum output swing to occur. Subsequently, the tradeoff between output swing and delay has been explored. We show that a 128×128 non-volatile capacitive crossbar array can be designed with >75mV swing and

A low-power fully differential level-crossing analog-to-digital converter (LC-ADC) for biomedical applications is presented. Different from conventional ADCs based on the uniform sampling rate, LC-ADC generates fewer samples for biomedical signals and leads to less power consumption in the following blocks. In this design, the power consumption of n-bit DAC and digital parts is reduced significantly with respect to the conventional LC-ADCs. The proposed method uses a charge redistribution block (CRB) instead of the n-bit DAC, which leads to a large reduction in average switching energy. Besides energy-saving, the proposed switching scheme also reduces the complexity of the controlling logic circuit, providing reduced complexity and low power consumption. Another advantage of the proposed LC-ADC is its fully differential structure. As a result, SNDR is improved by decreasing the levels of even harmonics. The proposed LC-ADC is designed in 0.18 um CMOS technology. Post-layout simulation results show an effective number of bits (ENOB) of up to 6.8 bits with about 97-188 nW power consumption under 0.8 V supply voltage and input signal bandwidth from 1 Hz to 4 kHz. The ADC occupies a silicon area of only 60×65 μm2.

Element matching approaches based on Optimal Combination Algorithms (OCAs) are methods that try to calibrate element mismatches in data converters by rearranging the mapping relations between circuit elements and control logics. This work for the first time proposes a universal method and its corresponding Figure-of-Merit to evaluate the performance of various OCA approaches. It adopts the quantile of integral nonlinearity as the criterion and is consequently compatible with most of matching OCAs. Dynamic performance and the corresponding effective-number-of-bits (ENOB) limited by mismatches are also investigated. A critical feature of the proposed method is its robustness to the disturbance of element standard deviation as long as the standard deviation is in a reasonable region. Merits of our method have been explained and proved mathematically, and also been verified numerically by data extracted from previously reported works and their reproduction by authors, which together make this proposal more convincing and rigorous. Due to those merits, our proposed method could also help designers to specify a feasible standard deviation for circuit elements when they are designing data converters with OCAs.

This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses V $_{{CM}}$ -based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm². At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are -0.65/+0.45 and -2.2/+2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.

This article presents an adaptive zoom-capacitance-to-digital converter (CDC)-based CMOS humidity sensor. The humidity sensor is realized by means of two differential capacitors whose dielectrics are sensitive to humidity. The sensing capacitors are interfaced with a zoom CDC, which consists of a successive-approximation-register (SAR) analog-to-digital converter (ADC) and a 3rd-order delta–sigma modulator ( $\Delta \Sigma \text{M}$ ). The SAR ADC eliminates the influence of the baseline capacitance to reduce the input range of the $\Delta \Sigma \text{M}$ . To improve the energy efficiency of the CDC across the full input range, a power-aware floating inverter amplifier (FIA) array is proposed, which is configured based on the conversion results of the SAR logic. In addition, an adaptive range-shift (ARS) zoom CDC is proposed to: 1) resist off-chip parasitics and interference and 2) allow low redundancy and a more energy-efficient FIA-based comparator, thus reducing power consumption. The proposed CMOS humidity sensor is implemented in a 0.11- $\mu \text{m}$ CMOS process. Measurement results show a capacitance resolution of 17.9 aF and an effective number of bits (ENOB) of 14.0 within a conversion time of 1.01 ms. The proposed humidity sensor consumes 1.5 $\mu \text{W}$ of power and exhibits a 0.0094 % relative humidity (RH) resolution and a ±1.5 %RH peak-to-peak accuracy (3 $\sigma $ error of 5.5 %RH) among 12 chips from 20 to 85 %RH, and it achieves a figure of merit (FoM) of 0.135 pJ $\cdot $ %RH 2 , which is more than six times better than the state of the art.

To design noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (ADCs) with high resolution and good power efficiency, two key bottlenecks need to be addressed. One is to realize a high-order loop filter with low circuit overhead, and the other is to mitigate the thermal noise. This article presents an NS-SAR ADC that synergistically addresses both challenges. To achieve high-order efficiency, it proposes an innovative error feedback-cascaded integrator feedforward (EF-CIFF) structure that realizes third-order noise shaping using only a single amplifier. It combines the merits of both structures, showing improved robustness, and is free of dc offset concern. On reducing the kT/C noise, this work features a sampling kT/C noise cancellation (SNC) technique that reuses the native hardware of the EF-CIFF structure. An open-loop self-quenching floating-inverter dynamic amplifier (FIDA) is used to support all amplification with low noise and power. Prototyped in 65-nm CMOS, this work achieves 84.8-dB signal-to-noise-distortion ratio (SNDR) with 625-kHz bandwidth (BW) (OSR = 8) and 119 $\mu \text{W}$ , leading to 182-dB Schreier Figure of Merit (FoM). It uses only 0.8-pF input capacitance, which is $5\times $ smaller than prior NS-SAR ADCs with similar oversampling ratio (OSR) and SNDR.

This paper presents a low power 12-bit 10-MS/s successive approximation register (SAR) analog-to-digital convert (ADC) for bio-signal signal processing in wearable sensor systems. A weighted sampling time technique applied to a capacitor digital to analog converter (C-DAC) is employed to reduce the power consumption of the conventional SAR ADC with minimum performance sacrifice. The proposed technique helped reduce its energy consumed by MSB, MSB-1, MSB-6, and MSB-7 capacitors by more than 40% compared with that of the conventional C-DAC. Another technique, a voltage scaling method is also employed to lower the power supply voltage from 1.2 to 0.6 V for all the digital logics except the output registers, such that it results in a power reduction of 70%. The proposed ADC is implemented with the standard CMOS 65 nm 1-poly 6-metal n-well process. The ADC achieves DNL/INL of ± 1.2LSB/ ± 1.5LSB, ENOB of 10.3-b, power consumption of 31.2 μW, and Walden FoM of 2.7fJ/step.

This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results.

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling.

We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

This brief proposes a high-speed and power-efficient multi-bit cyclic analog-to-digital converter (MC ADC) for CMOS image sensor applications. The proposed 13-bit MC ADC, which uses a 4-bit single-slope (SS) quantizer as a sub-ADC, resolves the sampled input voltage, followed by the cyclic SS quantization operation that repeatedly produces and quantizes the residue voltage. It operates in only seven phases to resolve 13-bit, thus achieving high conversion speed. Moreover, the 4-bit SS quantizer employs a simple and power-efficient structure that includes only the analog circuits of an operational amplifier and a comparator. A test chip with the proposed MC ADC was fabricated using a 0.18- $\mu \text{m}$ standard CMOS process technology. The measurement results show that the proposed MC ADC achieves a differential nonlinearity of +0.5/−0.54 LSB and an integral nonlinearity of +1.7/−2.8 LSB. In addition, the maximum signal-to-noise- and-distortion ratio and the effective number of bits are measured to be 73.14 dB and 11.86-bit, respectively. The measured power consumption per channel is only 87 $\mu \text{W}$ at a sampling frequency of 781 kHz. Moreover, the figure of merit (FoM), which includes the power consumption per channel, row line time, and ADC resolution, is only 13.6 fJ/conversion, achieving the best FoM among the compared works. Therefore, the proposed MC ADC is suitable for CMOS image sensor applications requiring high conversion speed and low power consumption, such as digital single-lens reflex cameras and ultra-high-definition television broadcast cameras.

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

A 10-bit 300 MS/s pipeline ADC utilizing time-domain MDAC is presented. The time-domain MDAC using only current sources and comparators to execute both signal subtraction and amplification is proposed to realize an opamp-less power-efficient structure without calibration. At the conversion rate of 300 MS/s with Nyquist input frequency, the ADC simulated in 40-nm CMOS exhibits an ENOB of 9.38 and 7.96 bits without and with device noise, respectively. It dissipates 19 mW at 1.2 V supply, where one-third of the power is consumed by the low-noise comparator. The noise analysis of the proposed time-domain MDAC is addressed. The active area of the ADC is 0.1 mm2.

The presented 16-channel $\Delta $ -modulated neural analog-to-digital converter (ADC) exhibits tolerance to input dc offsets of any value, up to the supply voltage. It employs a dynamic differential-difference comparator architecture with a super- $\text{G}\Omega $ input impedance ensuring negligible gate-leakage current and well-matched differential inputs resulting in more than 78 dB of rejection of common-mode signals and artifacts. The all-digital nature of the presented $\Delta $ -ADC enables sampling of input signals at high oversampling ratios (OSRs) making the front-end immune to stimulation artifacts with differential amplitudes up to a limit that is scalable by the OSR (e.g., 10 mVPP at OSR $=\,\,10$ k). Moreover, it allows the $\Delta $ -ADC to linearly scale down the power consumption required by the application’s recording bandwidth. The oversampled $\Delta $ -ADC achieves an effective number of bits (ENOB) of 9.7-bit and 2.6- $\mu \text{V}_{\mathrm {RMS}}$ integrated input-referred noise over 1 Hz to 500-Hz bandwidth. It uses no large passives or statically biased circuits, such as operational amplifiers (Opamps) saving both channel area (0.011 mm2) and power consumption (0.99 $\mu \text{W}$ ). Experimentally measured results validate the key features of the design and include in vivo recordings in freely moving guinea pigs. The fabricated prototype system-on-a-chip (SoC) hosts an array of 16-channel neural-ADC with in-channel digitally programmable high-compliance current-mode biphasic stimulators as well as wireless circuitry for data communication and power/command reception.

Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for complex, flexible, and robust signal processing algorithms in the digital domain, as well as easy implementation of advanced modulation schemes beyond binary PAM2. However, the power consumption of the ADC and ensuing digital equalization is a key issue for such receivers in high-speed applications. Embedding analog equalization inside the ADC architecture allows for both a lower ADC resolution and a reduced-complexity digital equalizer, resulting in a more power-efficient receiver. This article presents a 6-bit 1.5-GS/s time-interleaved successive approximation register (SAR) ADC with low-overhead two-tap embedded decision-feedback equalizer (DFE). A smart speculative DFE is proposed to reduce additional conversion cycles required for the equalization realization in the ADC. Moreover, DFE functions are efficiently embedded in the capacitive digital-to-analog converter (DAC) references. The prototype ADC with two-tap DFE is implemented in a 130-nm CMOS process and achieves a 5.24-bit peak effective number of bits and 0.59-pJ/conversion-step figure-of-merit (FOM) at a 1.5-GS/s sampling rate while consuming 34.1 mW and occupying a core area of 0.32 mm2. The effectiveness of the embedded DFE in timing margin improvement is verified for 1.5-Gb/s operation over high-loss FR4 channels at a bit error rate (BER) of 10−9.

A broadband digitizer is proposed and experimentally demonstrated based on photonic time stretch (PTS). In this scheme, a complementary single-sideband modulation architecture in combination with successive digital difference operation and phase compensation are employed to simultaneously eliminate dispersion-induced power fading problem, remove dynamic pulse envelope, suppress modulation nonlinearity impairment and maintain broadband waveform fidelity. In the proof-of-concept experiment, a PTS preprocessor with a stretch factor of 8.77 and a time window of 1.8 ns is realized, where the maximum power degradation in the frequency range up to 25 GHz is 5 dB. By using this preprocessor, single-tone microwave signals in the frequency range of 2 to 25 GHz are digitized with effective number of bits larger than 3.4 bits. For single-tone input microwave signals at 12 and 15 GHz, the 2nd-order harmonic suppression ratios are enhanced by 11.51 and 16.86 dB, respectively. For a two-tone microwave signal at 8 and 10 GHz, the synthetic waveform fidelity after time stretch is maintained by carrying out phase compensation.

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

This article introduces a re-configurable pipeline analog-to-digital converter (ADC) deliberated for implantable surveillance devices for bio-impedance monitoring systems. To improve the efficiency of the bio-impedance method, an automatic adaptation circuit is introduced. This adaptive unit is responsible for setting the resolution and sampling rate on the basis of amplitude and frequency of the signal. Using a new, low-power automatic adaptation circuit low power consumption is achieved by using Dynamic Threshold metal oxide semiconductor (DTMOS) technique, it can automatically determine its setup. The converter has two modes of operations. In high-resolution mode, the converter has a 12-bit resolution and at low resolution mode, 8-bit resolution is used. The ADC bandwidth of low-speed mode is 100 kHz and high-speed mode is 1 GHz. The architecture is designed using 180 nm technology and simulated using Cadence virtuoso tool. The results achieved, low power consumption i.e. 0.844 mw, and it is operated with 1 V power supply. For signal to noise and distortion ratio (SNDR), effective number of bits (ENOB), the converter utilizes 71.06 dB, 11.45 in 12-bit and 72.3 dB, 7.41 in 8-bit mode respectively. By using proposed method around 20% of power consumption is reduced and 40% power supply is decreased. The proposed design is also used for mixed signal circuit testing.

A novel energy-saving and area-efficient tri-level switching scheme is proposed for successive approximation register analog-to-digital converters (SAR ADCs). Different from most published tri-level switching schemes, a new third reference voltage Vaq which equals to 1/4 Vref is applied to the proposed scheme. And benefiting from Vaq, the proposed scheme achieves 87.5% capacitor area reduction over the conventional scheme. Due to the capacitor-splitting structure and top-plate sampling, the switching energy is negative during the first three switching cycles, which means the capacitor arrays return energy back to the reference voltages and results in significant energy saving. For a 10-bit SAR ADC, the average switching energy of proposed scheme is only 5.3 $$CV_{{{\text{ref}}}}^{2}$$ , which realizes 99.61% energy saving compared with the conventional scheme. Moreover, the proposed scheme is of low control logic complexity since single-side switching is applied during the remaining switching cycles. Therefore, the proposed scheme achieves a good trade-off among energy saving, area efficiency and logic complexity. For a 10-bit SAR ADC, the simulated differential nonlinearity (DNL) and integral nonlinearity (INL) with 1% capacitor mismatch are 0.322 LSB and 0.321 LSB, respectively. Considering 0.3% reference voltage mismatch, the mean values of effective number of bits (ENOB), signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) are 9.77 bit, 60.57 dB and 75.43 dB, respectively, through 500 Monte Carlo simulations. To verify the feasibility of circuit implementation, transistor level simulation of a 0.6-V 10-bit 200-KS/s SAR ADC in 40-nm CMOS technology is performed. The ENOB, SNDR and SFDR of SAR ADC with 98.83-kHz Nyquist rate input are 9.66 bit, 59.90 dB and 71.98 dB, respectively.

The article proposes an approach to increasing the resolution of integrated analogue-to-digital (ADC) converters with intermediate voltage-to-frequency conversion (VFC). At sampling rate1 kHz was achieved effective number of bits (ENOB) from 12 to 16. In addition, an approach to compensating for the non-linearity of voltage-to-frequency conversion was proposed. Across the range of measured voltages from 100 mV to 8 V, the voltage measurement error comprised no more than ±0.025 %, which corresponds to a five-and-a-half-bit voltmeter. The proposed device was implemented exclusively on mass-produced chips. The six independent ADC channels, implemented on 1316PP1AU VFCs, are serviced by a single 1986VE91 microcontroller, with the processor loading with the task of improving accuracy being no more than 10%.

This study proposes the design of a light to digital converter (LDC) for the long-time continuous monitoring of the photoplethysmography (PPG) signal. The design system incorporates a transimpedance amplifier (TIA), a delta-sigma modulator (DSM), and a decimation filter. The analog front-end circuit is implemented in the integrated chip with the chip area of 2.76 mm2 and fabricated via TSMC T18 process. The standard supply voltage used for the experiment is 1.8 V. The measurement result shows that the TIA – 3 db gain is 100 dB gain and – 3 dB cutoff frequency is 110 kHz. The design delta-sigma modulator can achieve the signal to noise plus distortion ratio (SNDR) of 50 dB at – 10 dB of the input signal. The measured signal to spurious-free dynamic range (SFDR) of the DSM is 50 dB. The measured effective number of the bit is (ENOB) of 8.3 bits. The on-chip 4th order decimation filter is used herein to convert the one-bit output of the DSM to the multibit output with a down sampling rate of 64 Hz. The measured cutoff frequency of the decimation filter is 10 Hz, and the operating sampling frequency is 1280 samples/seconds. Therefore, the overall designed bandwidth of the design system is 10 Hz bandwidth. The power consumption of the whole circuit is less than 100 µW. The achieved bandwidth of 10 Hz is the best among all the reported to date.

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cyclic-coupled ring oscillators (CCROs) as a time-domain quantizer to achieve a combination of subgate-delay time resolution together with a short conversion time, thereby enabling data conversion with high resolution as well as high bandwidth. The resolution-power tradeoff in coupled oscillators is studied. Simulation indicates up to a factor-of-13 subgate-delay time resolution with 13 coupled oscillators. A real-time quantizing time-to-digital converter with coupled oscillators is designed for a time-domain analog-to-digital converter. Powered by a factor-of-8 subgate-delay time resolution of 1.6 ps obtained with nine coupled oscillators, and a sample time of 4 ns for 11-bit conversion, the converter delivers a 9.9-bit ENOB over a signal bandwidth of 125 MHz and an SFDR of 88 dB. Results demonstrate that CCROs is an attractive candidate as a high-precision high-linearity time-domain quantizer for data converters.

This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling speed. The linearity of the CDAC is calibrated by programming the least-significant-bits (LSBs) dummy capacitor. The unit capacitor in the CDAC array is customized for higher symmetry and reducing their mismatch. Our SAR ADC is based on asynchronous logic, and its timing is controlled by a delaying block in the critical path. The prototype is fabricated in a 65-nm CMOS process with a 1.2 V supply and occupies an active area of 0.029 mm2. With a 100-MS/s sampling rate, the measured ENOB scores 10.17 bits for 1.5 MHz input with a figure-of-merit (FoM) of 6.94 fJ/conversion-step. It can achieve 8.83 bits for Nyquist input signal.

During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 mm2.

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a pulse-shrinking inverter-assisted residue quantizer (IRQ). Previous pulse-shrinking techniques suffer from a nonuniform shrink rate and time offset that slows the conversion and increases power consumption. The proposed pulse-shrinking IRQ reduces the time difference between residue signals instead of shrinking the pulse width. This approach achieves a high resolution with low power consumption and a high conversion rate. The critical tradeoff between resolution and dynamic range (DR) is addressed using a three-step cyclic conversion approach: coarse, fine, and residue quantization steps. The adverse effect of the oscillator startup time on linearity is analyzed, and a correction method is proposed using both on-chip circuit design and off-chip data processing. The proposed TDC is fabricated using a 180-nm CMOS process in a core area of 0.11 mm2. The TDC can be configured into one of four resolution modes, 36, 64, 89, and 135 ps, at conversion rates of 0.82, 1.29, 1.47, and 1.86 MS/s, respectively. A wide DR of up to 179 ns is achieved. The linearity is well performed with a maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of 0.4/0.73 LSB at a conversion rate of 1.86 MS/s. An effective number of bits, $N_{\mathrm {linear}}$ up to 9.88-bit, and a figure-of-merit (FoM) down to 0.31 pJ/conversion are achieved by consuming 0.55 mW.

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC’s channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator’s offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18- $\mu \text{m}$ 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as −0.4/0.54 and −0.81/0.89 LSB, respectively, where $1\,\,\text {LSB} = 0.488$ mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC) exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) implemented in 28-nm CMOS. In the proposed technique, the Dickson CP generates a ramp signal that is compared with the input voltage to generate a pulse of commensurable widths, which is then fed to a D-type flip-flop (DFF)-based time-to-digital converter (TDC). The TDC is composed of CMOS DFFs and digital circuits for digital conversion without any use of analog-intensive circuits, e.g., amplifiers or current sources. Thanks to the robustness of Dickson CP characteristics, the digital outputs of the proposed ADC can be corrected through a low-complexity deterministic digital mapping with improvements of 1.5-bit in peak effective number of bits (ENOB) and 9 dB in peak signal-to-noise-and-distortion ratio (SNDR) verified over three measured sample prototypes.

A single-chip Gaussian monocycle pulse (GMP) transceiver was developed for radar-based microwave imaging by the use of 65-nm complementary metal oxide semiconductor (CMOS) technology. A transmitter (TX) generates GMP signals, whose pulse widths and -3 dB bandwidths are 192 ps and 5.9 GHz, respectively. A 102.4 GS/s equivalent time sampling receiver (RX) performs the minimum jitter, input referred noise, signal-to-nose-ratio (SNR), signal-to-noise and distortion ratio (SNDR) effective number of bits (ENOB) of 0.58 ps, 0.24 mVrms, 28.4 dB, 26.6 dB and 4.1 bits, respectively. The SNR for the bandwidth of 3.6 GHz is 36.3 dB. The power dissipations of transmitter and receiver circuits are 19.79 mW and 48.87 mW, respectively. The GMP transceiver module can differentiate two phantom targets with the size of 1 cm and the spacing of 1 cm by confocal imaging.

A novel digital adaptive blind calibration technique for frequency-interleaved analog-to-digital converters (FI-ADCs) with arbitrary numbers of channels is proposed. It performs the estimation and correction of multiple inherent circuit deficiencies alternately and recursively in the background, including spectral leakage, harmonic folding, jitter, I/Q mirror and aliasing images, and suffices to deliver projected calibration capabilities with deliberately chosen initial guesses. We are of the opinion that this is the first study to address the joint channel identification and error compensation problem encountered in the FI-ADC design. For the efficient implementation, an analytical time-interleaving-like equivalent model is formulated such that the number of unknown mismatch parameters is significantly reduced, and signals devoted to cyclic estimation are maximally decimated. This derived model not only propounds a better perspective for comprehension and interpretation of the FI system mechanism but also enables sufficient scalability and flexibility of the developed calibration framework. Extensive simulation results further show that this novel architecture achieves a good balance between the computational complexity and convergence, and provides an exceptional and relatively flat effective number of bit (ENOB) performance over a wide bandwidth.

This brief proposes a new low-power time-to-digital converter (TDC). In contrast to the previous works that digitize each new input sample independent of the previous ones, the proposed structure obtains the digital code of the new sample based on the difference between the previous sample and the new one. Therefore, since the activity of the circuit is reduced, its power consumption is saved, especially for the applications that the variation of the input signal is usually much smaller than the signal range, such as sensor interface circuits. Based on the proposed structure, a 200 kS/s TDC circuit with a resolution of 3.2 ps is designed and simulated in a 65-nm CMOS technology. Post-layout simulation results show that the proposed structure achieves an effective number of bits (ENOB) of 7.52 bits at the cost of 10.1 $\mu \text{W}$ power consumption. Moreover, the effective area occupied by the circuit is 110 $\mu \text{m}\,\,\times $ 130 $\mu \text{m}$ .

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

In the modern era of artificial intelligence, increasingly sophisticated artificial neural networks (ANNs) are implemented, which pose challenges in terms of execution speed and power consumption. To tackle this problem, recent research on reduced-precision ANNs opened the possibility to exploit analog hardware for neuromorphic acceleration. In this scenario, photonic-electronic engines are emerging as a short-medium term solution to exploit the high speed and inherent parallelism of optics for linear computations needed in ANN, while resorting to electronic circuitry for signal conditioning and memory storage. In this paper we introduce a precision-scalable integrated photonic-electronic multiply-accumulate neuron, namely PEMAN. The proposed device relies on (i) an analog photonic engine to perform reduced-precision multiplications at high speed and low power, and (ii) an electronic front-end for accumulation and application of the nonlinear activation function by means of a nonlinear encoding in the analog-to-digital converter (ADC). The device, based on the iSiPP50G SOI process for the photonic engine and a commercial 28 nm CMOS process for the electronic front end, has been numerically validated through cosimulations to perform multiply-accumulate operations (MAC). PEMAN exhibits a multiplication accuracy of 6.1 ENOB up to 10 GMAC/s, while it can perform computations up to 56 GMAC/s with a reduced accuracy down to 2.1 ENOB. The device can trade off speed with resolution and power consumption, it outperforms its analog electronics counterparts both in terms of speed and power consumption, and brings substantial improvements also compared to a leading GPU.