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Assuming negligible in-plane stress, non-varying shear stress, and linearly varying transverse stress along the thickness of the adhesive, the closed-form solutions for the interfacial shear and the interfacial peeling stresses in balanced bonded sandwich structures was derived. The nil-shear-stress condition at the free edge of the adhesive was enforced through the use of a decay function. The solutions for the shear and the peel stresses along the interfaces right up to the free edge were validated with the finite element analysis. The solutions were used to investigate (i) the observed increase susceptibility of single lap joints with increase bondline thickness and (ii) the nil report of such susceptibility for electronic assemblies experiencing differential thermal strain. The first investigation was compromised by the inability of the solutions to model the singular stress/strain field at the free-edge of the interfaces. The second investigation revealed a far higher rate of reduction in the magnitudes of the interfacial shear and peeling stresses in structures (electronic assemblies) that experience differential thermal strain than in structures (single lap joints) that experience bending strain.

Background The existing creep-fatigue models are valid over limited ranges of temperatures and frequencies. Need There is a need to develop a creep-fatigue equation that covers the full range of phenomena from pure fatigue to pure creep rupture, and all the intermediate failures. Method By integrating the Manson-Haferd parameter into the Coffin-Manson equation, the creep-integrated fatigue equation is developed and further is validated on three metal alloys: 63Sn37Pb solder, Sn3.5Ag solder and stainless steel 316. Results This new formulation collapses the dispersed strain-life data of the alloys obtained at diverse temperatures and cycle times into a cohesive strain-life formulaic representation. Supported by this result, the method of establishing the material parameters for the creep-integrated fatigue equation is demonstrated. Originality The resulting equation is capable of modelling the full range of creep-fatigue interaction from pure fatigue to pure creep rupture, and the combinations thereof. A method is provided to determine the coefficients.

We have investigated the possible oscillation of linear and non-aging viscoelastic functions of viscoelastic models whose governing differential equations representing the constitutive relation between stresses and strains are of second order. We have found that the Stieltjes inverse of the time-dependent Poisson ratio could be oscillatory for engineering materials whose bulk and shear relaxation moduli are monotonically decreasing.

Compared to the theory of elasticity solutions the strength of material solutions offer closed form solutions that is favoured by practising engineers for performing design analysis. However, the existing strength of material solutions for a sandwich structure experiencing differential thermal strains have principally ignored the free edge conditions; and for the very limited publications that have enforced the free edge conditions, the solutions have been inaccurate. Understandably, design analysis using such solutions is unreliable. This manuscript describe a solution technique that enforces the nil shear stress condition at the free edge using a high power exponential function resulting in a simple yet accurate closed form solutions for the interfacial shear stress. The interfacial peeling stress is made up of two components: the mean and the amplitude of variations of the transverse normal stress in the bonding layer; the latter is the dominant component whose magnitude is linearly proportional to the gradient of the interfacial shear stress. Following validation by finite element analysis, design analysis for debonding, fracturing, and out-of-plane deformation are performed using the concise closed form solutions.

Through sequential coupling of the differential equations for interfacial shearing and peeling stresses, concise closed-form strength-of-material solutions for these stresses in symmetric and non-symmetric sandwich structures subjected to the combined loadings of temperature, stretching, and bending have been developed. The free-edge effects of the interfacial shearing stress, the maximum magnitude of the interfacial shear stress, and the location of its occurrence are accurately modelled using a single high-frequency hyperbolic function. The analytical solutions have been validated against finite element analysis (FEA) solutions using four sandwich structures: one symmetric, two mildly asymmetric, and another severely asymmetric; and for three load cases: differential thermal expansion, differential mechanical stretching, and mechanical bending. The maximum deviation between the analytical and the FEA solutions for the interfacial shearing and peeling stresses for all the structures and load cases, including that for the severely asymmetric sandwich structure, was less than 15%.

A two-step solutions is used to model the stresses in the discrete joints of a sandwiched structure due to mismatched thermal expansion. In the first step, the discrete joints are modelled as elastic body with nil lateral stiffness, the stretch and shear stiffness of which are equivalent to that of the solder joints smearing across the entire layer. Through the introduction of a high-order frequency function, interfacial shear and peeling stresses with the correct free-edge effects are derived. In the second step, the interfacial stresses are integrated into forces and are applied to the discrete joints to obtain the mean stresses; this is followed by modification of the mean shear stress using the high-order frequency function to impose the nil-shear-stress condition at the free-edge of the discrete joints. The closed-form solutions have found good agreements with the numerical solutions.

The existing analytical solutions for the peeling and shearing stresses in polymeric adhesively bonded structures are either too inaccurate or too complex for adoption by practicing engineers. This manuscript presents a closed-form solution that is reasonably accurate yet simple and concise enough to be adopted by practicing engineers for design analysis and exploration. Analysis of these concise solutions have yielded insightful design guidelines: (i) the magnitude of peeling stress is generally higher than that of shearing stress; (ii) the peeling stress in a balanced structure may be reduced most effectively by reducing the elastic modulus of the adherends or by increasing the adhesive-to-adherend thickness ratio and less effectively by reducing the elastic modulus of the adhesive; and (iii) the peeling stress in an unbalanced structure may be reduced by increasing the in-plane compliance of the structure, which may be implemented most effectively by reducing the thicknesses of the adherends and less effectively by reducing the elastic modulus of the adherends. Published version

“Pure fatigue” is a special case of creep-fatigue; and the Coffin–Manson equation, Δ e p = C o N - β o , is a special case of the general creep-fatigue equation, which is proposed to take the form: Δ e p = C o s ( σ ) c ( T , f ) N - β o b ( T , f ) . The functions, s(σ), c(T, f) and b(T, f), embody the stress–time–temperature characteristic of creep. At the reference condition when creep is dormant, s(σ) = c(T, f) = b(T, f) = 1, the Coffin–Manson equation is recovered. At the extreme condition when c(T, f) = 0, creep-rupture occurs without fatigue. In between these two extreme conditions whence 0 ⩽ c(T, f) ⩽ 1, creep-fatigue prevails.

A new representation for viscoelastic functions, the tensor relaxation-creep duality representation, is introduced. The derivation of a tensor time-differential constitutive equation for anisotropic viscoelastic materials using this new presentation is presented. The relaxation-creep duality characteristic ingrained in the new representation enables the interconversion of viscoelastic functions, which is not possible with the conventional Prony series representation of viscoelastic functions. The new representation therefore offers a better representation of the physics of viscoelasticity leading to a reduced number of viscoelastic parameters required to describe a viscoelastic function. The new representation has been demonstrated on two anisotropic viscoelastic crystallographic systems: (i) the symmetric systems with material- and time-independent eigenvectors and (ii) the symmetric systems with material-dependent but time-independent eigenvectors.

The effects of different pin features and dimensions of scrolled shoulder bobbin friction stir welding were tested for welding marine grade aluminium, Al6082-T6. Welds were created in longitudinal and transverse plate extrusion directions in thin plate aluminium clamped and supported at one side. Measured outcomes included visual inspection, plate distortion, mechanical properties, metallurgical examination, and hardness test. This study shows that tool features cannot be directly transferable from conventional friction stir welding technology without comprising process variables and tool part functionality. Process setting such as clamps, support arrangements, shoulder gap and welding direction create compression, vibration and heat distribution hence influence the weld quality. The best joint was produced by four flats tool pin followed by threaded tool pin with three flats. These findings were used to develop a conceptual theory representing the underlying physics of the friction stir welding process. The effects of pin features, specifically threads and flats, are identified. This model is useful for direct linking welding factors towards the expected consequences.

The low-cycle strain–life characteristic of solder joint formed by reflowing Sn1.0Ag0.1Cu solder onto copper pad has been investigated at the high cyclic frequency regime between 30 Hz and 150 Hz. Expressing the strain–frequency-life relation of the solder joint as e pcb f q = m o N α λ , the frequency exponent q has been evaluated to be 0.34, implying decreasing fatigue life with increasing cyclic frequency, in opposite trend to creep–fatigue. Analysis of the test system has suggested that while the stresses experienced by the solder joints increases only marginally with increasing frequency, the fatigue strength of the solder joint decreases drastically with increasing frequency – due to reduction in the fracture toughness of solder joints with increasing strain rate – giving rise to a net reduction in fatigue life of the solder joint.

This manuscript presents a systematic derivation of novel creep-integrated fatigue equations that possess the following unique characteristics: (i) creep damage and creep-fatigue interaction damage are embedded into the fatigue equation and requires no deliberate computation; (ii) the embedded creep damage is formulated from the constitutive equation of creep; and (iii) the integrated equation is capable of modelling the full range of creep fatigue from pure creep to pure fatigue. These characteristics ensure that these creep-integrated fatigue equations are fundamentally sound, easy to use, and applicable over a wide range of creep fatigue conditions. The creep-integrated fatigue equations based on three constitutive equations of steady-state creep: Dorn equation, Larson-Miller equation, and Manson-Haferd equation are derived and successfully validated using two metals of vastly different creep and fatigue characteristics – the SS316 stainless steel and the Sn37Pb solder.

The low-cycle-fatigue characteristics of solder joints, formed by reflowing Sn98.8/Ag1.0/Cu0.1/In0.05/Ni0.02 solder over electroless nickel immersion gold-plated copper pads, were investigated by dynamic cyclic bending of printed circuit boards (PCBs). The PCB strain amplitudes were varied from 1.2 × 10−3 to 2.4 × 10−3 and the flexural frequencies ranged from 30 Hz to 150 Hz, to simulate drop impact-induced PCB resonant frequencies. A trend of drastically decreasing fatigue life with cyclic frequency was observed, in contrast with previous reports indicating the reverse; this is attributed to the different failure mechanisms activated. A systematic procedure involving optimization followed by transformation was used to condense the strain–frequency–life data into a master curve expressed in strain–life space.

The monotonicity of the linear viscoelastic functions, namely, the shear creep compliance, the Young’s relaxation modulus, the stretch creep compliance, the P-wave relaxation modulus, the Lamé’s first function, and the time-dependent Poisson’s ratio, were examined analytically and numerically. It was shown that both the Lamé’s first function and time-dependent Poisson’s ratio can be non-monotonic. Furthermore, in contrast to the reports by other researchers, the values of the time-dependent Poisson’s ratio were found to be bounded by the limits between −1 and 0.5 after the physical constraints of the bulk and shear relaxation moduli are taken into account.

The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimize the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines crack-front mapping using the dye and pry method and electrical FE simulation to establish a relation between DC electrical resistance and cracked area, and hence monitor the initiation and propagation of cracks in individual solder joints as the PCB assemblies are subjected to JEDEC type mechanical shock and high speed cyclic bending. The carrier in the study is a ball grid array (BGA), a critical component family for drop impact. Combinations of solder alloys and pad finishes, SnPb on organic solderable preservative (OSP), SAC305 on electroless nickel/immersion gold (ENIG), SAC101 on OSP, and SAC101(d) on ENIG are studied regarding the failure mode and crack propagation. This paper demonstrates that, for the large majority of Pb-free solder joints, there is a negligible initiation period; cracks can start forming at the first PCB bending cycle. The presence of large cracks, especially at both sides can increase the compliance of the joint and slow down crack growth. Even if large cracks are present, the resistance increase is less than 1 m? per interconnect, which is far from the 100 ? that is often taken as a failure criterion. Brittle joints as found with SAC305 on ENIG have erratic propagation rates while ductile joints are much more predictable. Therefore, the way to optimize the drop test performance of a Pb-free BGA assembly is to prolong the crack propagation within the ductile bulk solder material.

Thermal stress due to mismatched thermal expansion is a problem that has challenged the electronics packaging industry for decades. Analytical solutions are available in the literature for a tri-material in which the sandwiched layer is an adhesive, but the solutions may not be suitable for a sandwiched layer consisting of discrete elements such as solder joints which experience significant bending. In this paper, closed-form analytical solutions have been developed for both continuous and discrete sandwiched layers by modelling the interconnects as a slab of spring elements capable of transferring axial, shear, and bending load. The analytical solutions have been successfully validated with finite element analysis.

Half-sine acceleration-shock is prescribed to the supports of the printed circuit board (PCB) in the JEDEC JESD22-B111 test standard, which is used to evaluate the reliability of the board level solder joints to mechanical shock. In practice, it is near impossible to introduce an acceleration-shock of perfect half-sine and distorted excitations are common. This inconsistency is believed to be responsible for the poor reproducibility of the JEDEC test, yet there has been no serious attempt to investigate the effects of such distortion to the responses of the PCB. In this article, the distortion of the excitation was quantified and analytical solutions were developed for the distorted PCB responses by expressing the distorted excitation using Fourier series of odd function. The magnitude of distortion in the response of the PCB-measured by the percentage deviation in the amplitude of the distorted response from the ideal response-was found to be quantitatively equivalent to the magnitude of distortion in the half-sine excitation-measured by the percentage deviation in the enclosed area of the distorted excitation from the ideal half-sine excitation. Without proper control of the quality of the half-sine excitation, drop tests based on JEDEC JESD22-B111 performed at two different sites could produce PCB responses that are significantly different. To improve the reproducibility of the test, the surface strain on the PCB should be specified as the key test parameter, supplemented by the half-sine acceleration-shock of specified duration, leaving the amplitude adjustable to meet the desired surface strain on the PCB.

The increasing occurrence of drop-impact failure of portable electronics could be traced to the failure of the solder joints that interconnect the integrated circuit (IC) components to the printed circuit board (PCB)—collectively referred to as PCB assembly. The drop impact leads to bending of the PCB assembly within the portable electronics, and the interconnecting solder joints undergo severe deformation to accommodate the differential bending deformation between the IC component and the PCB. This manuscript presents an approximated closed-form analytical solution for the stresses in the solder joints of the PCB assembly subjected to mechanical bending. The PCB assembly is modelled as a tri-layer structure in which the IC component and the PCB are modelled as beams or plates and the solder joints as a continuous layer consisting of infinite number of beams that are capable of carrying normal force, shear force, and moment along its interfaces with the IC component and the PCB. The analytical solutions have been validated against finite element analysis. Design analysis has suggested that the robustness of the PCB assembly against mechanical bending can be increased by increasing the diameter of the solder joints; increasing the in-plane and flexural compliances of IC component and PCB; while reducing the shear and flexural stiffness of the solder joints and reducing the transverse compliant of the PCB assembly.

The fatigue crack growth in a solder joint was monitored during dynamic cyclic loading induced by mechanical shock. Crack growth was tracked via measurement of tiny resistance changes in the solder joint coupled with computational simulations of cracked joints. The unique fatigue characteristics observed are an insignificant crack nucleation period and a distinctive growth pattern for bulk solder cracks. Crack growth accelerates upon movement of the crack into intermetallic regions, a common occurrence for lead-free solders under high material strain rates.

Thermal stress has been a concern in electronic packaging for decades. More recently, mechanical bending of printed circuit board (PCB) assembly has attracted increased interest due to the drop impact failure of interconnects in mobile products. Analytical solutions are available in the literatures for a PCB assembly modeled as a tri-layer structure, consisting of IC components, PCBs, and an interconnect layer, subjected to either thermal stress or mechanical bending, but there are no known reports for combined loadings. This paper presents a comprehensive treatment for a PCB assembly subjected to combined temperature and mechanical loadings, taking into account the axial, shear, and flexural deformation of the interconnects. Solutions are provided for two types of interconnect layer: one in which the interconnect layer is made of a continuous element such as adhesive, and another in which the interconnect layer is made of discrete elements such as solder joints. The solutions were successfully validated with finite-element analysis, and design analyses were performed for both types of interconnect layers.

This paper presents a comprehensive methodology to model the static temperature-humidity (TH) aging test ( 85 degC/85%RH over 1000 h) of flip chip on flex interconnections with nonconductive adhesives (NCAs). NCAs, being a special form of conductive adhesives, are chosen, as they allow bringing the pitch further down. The methodology combines experimental techniques for material characterization, finite element modeling (FEM), and model validation. A NCA has been characterized using several techniques. The thermomechanical properties and the moisture absorption properties were obtained for the NCA. A temperature dependent viscoelastic constitutive model was also obtained for the NCA. The viscoelastic model was defined by the Prony series expansion. The shift factor was approximated by the Williams-Landel-Ferry (WLF) equation. Finite element modeling has been performed to analyze the flip chip interconnects on flex with the NCA under process condition and reliability aging conditions. The viscoelastic constitutive relation has been used to model the NCA in aging modeling. An integrated process-aging modeling methodology has been developed to combine the thermo-mechanical stress and hygro-mechanical stress, followed by stress relaxation analysis. To verify the finite element models, static TH aging tests (85 deg C/85%RH) were also performed. The contact resistance was monitored with high measuring resolution during the accelerated test. The simulation results are in good agreement with the experimental results. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters to achieve good reliability performance.

Drop impact reliability has become an important criterion when assessing the reliability of portable electronics. Finite element software such as ABAQUS is used to simulate solder joints during drop-impact tests and determine the drop-impact reliability of the product. This modelling requires the rate-dependent constitutive properties of the solder in the range of strain rates between 0.1 s− 1 to 300 s− 1. Unfortunately, the constitutive properties of most solder materials in this range of strain rates have not been characterized. This paper presents the mechanical properties of four solder alloys — 63Sn37Pb, Sn1.0Ag0.1, Sn3.5Ag, and Sn3.0Ag0.5Cu at strain rates between 0.005 s− 1 and 300 s− 1. The lead-free solder alloys tested exhibited greater strain rate sensitivity compared to 63Sn37Pb. In addition, both the lead-free solders with high Ag content (≥ 3%) exhibited much higher flow stresses compared to 63Sn37Pb. The higher flow stress could explain the lower reliability of these joints in drop tests as a result of shifting of the failure site from the ductile solder to the brittle intermetallic compound [Wong EH, Rajoo R, Mai Y-W, Seah SKW, Tsai KT, Yap LM. Proc. 55th Elec. Comp. & Tech. Conf. 2005;1202–9]. Based on the data obtained, Sn1.0Ag0.1 seems to be the most suitable lead-free alloy to replace eutectic tin-lead in products where drop-impact performance is required.

A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps.

The stress–strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 s−1 and 300 s−1 are required to support finite-element modeling of the solder joints during board-level mechanical shock and product-level drop-impact testing. However, there is very limited data in this range because this is beyond the limit of conventional mechanical testing and below the limit of the split Hopkinson pressure bar test method. In this paper, a specialized drop-weight test was developed and, together with a conventional mechanical tester, the true stress–strain properties of four solder alloys (63Sn-37Pb, Sn-1.0Ag-0.1Cu, Sn-3.5Ag, and Sn-3.0Ag-0.5Cu) were generated for strain rates in the range from 0.005 s−1 to 300 s−1. The sensitivity of the solders was found to be independent of strain level but to increase with increased strain rate. The Sn-3.5Ag and the Sn-3.0Ag-0.5Cu solders exhibited not only higher flow stress at relatively low strain rate but, compared to Sn-37Pb, both also exhibited higher rate sensitivity that contributes to the weakness of these two lead-free solder joints when subjected to drop impact loading.

Thermal stress due to mismatched coefficients of thermal expansion is a problem that has challenged the electronics packaging industry for decades. Analytical solutions are available in the literatures for a tri-material in which the sandwiched layer is a continuous layer. This author has earlier presented a solution for the sandwiched layer constituted of discrete interconnects; however, the solution ignores the shear deformation of the substrate layers. This paper removes the above assumptions and provides closed-form solutions for the shear, bending, and axial stresses in the sandwiched layer, as well as the in-plane stress in the substrate layers. The solutions are applicable to printed circuit board (PCB) assemblies constituting of an integrated circuit (IC) component, solder joints, and the PCB or to an IC component of tri-material layer structure. The solutions have been successfully validated with finite element analysis. Design analyses based on the analytical solutions have been performed for the shear and peeling stresses in the interconnects, the tensile fracture of IC chips due to in-plane stress, and the warpage of the IC component.

Closed form analytical solutions for the stresses in the interconnects between the integrated circuit (IC) package and the printed circuit board (PCB) when the PCB assembly is subjected to a mechanical shock have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnects when subjected to mechanical shock, and have been used to establish the following key findings: 1) for the same magnitude of strain measured on the PCB, symmetric bending will result in the highest stress in the interconnect while anti-symmetric bending will result in the least stress; 2) the cross-section area of the interconnect is the single most critical parameter; 3) the eight-layer buildup board specified in JEDEC standard JESD22-B111 can be replaced with an equivalent conventional board that exhibits similar natural frequency as the eight-layer buildup board.

Non-conductive adhesive (NCA) flip-chip interconnects are emerging as an attractive alternative to lead or lead-free solder interconnects due to their environmental friendliness, lower processing temperatures, and extendability to fine-pitch applications. The electrical connectivity of an NCA interconnect relies solely on the pure mechanical contact between the integrated circuit (IC) bump and the substrate pad; the electrical conductivity of the contact depends on the mechanical contact pressure, which in turns depends to a large extent on the cure shrinkage characteristics of the NCA. Therefore, it is necessary to monitor the evolution of the electrical conductivity which could reflect the impact of cure- and thermal-induced stresses during the curing and cooling process, respectively. In this article, in situ measurement of the development of contact resistance during the bonding process of test chips was developed by using a mechanical tester combined with a four-wire resistance measurement system. A drop of resistance induced by the cure stress during the bonding process is clearly observed. With decreasing bonding temperature, the drop of contact resistance induced by cure shrinkage becomes larger, while the cooling-induced drop of resistance becomes smaller. The evolution of contact resistance agrees well with experimental observations of cure stress build-up. It is found that vitrification transformation during the curing of the adhesive could lead to a large cure stress and result in the reduction of the contact resistance. Furthermore, no obvious changes were observed when the applied load was removed at the end of bonding.

Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders

Summary: Significant stresses develop during cure in functional and structural applications of polymeric materials ranging from glass fiber composites to advanced functional polymers used in microelectronics, optoelectronics, and biomaterials applications. These stresses arise from a combination of chemical shrinkage and stiffness buildup in a confined geometry. In this paper, a new method for direct measurement of cure-induced stresses during curing of thermosetting materials by using the iso-strain mode of a dynamic mechanical analyzer (DMA) has been developed. A thermal tape was used to facilitate maintaining a constant strain and initiate the iso-strain measurement. Two quartz rods with a small gap were used to contain the material. The top of the quartz rod and one side of the thermal tape were secured by the fixed clamp, while the bottom quartz rod and the other side of the thermal tape were clamped with the moveable force probe. The cure force was thereby directly measured by the probe during the curing process. The cure stress buildup was observed to occur after a certain duration that corresponds to the gel point. Experimental results clearly show that curing at lower temperature could lead to higher cure stress due to the earlier onset of vitrification. An investigation of the stress buildup as a function of degree of cure indicates that a majority of the cure stress was generated in the vitrification regime. The methodology proposed herein provides an accurate experimental approach to investigate the cure-induced stress generated in a thermosetting material in applications ranging from microelectronics and optoelectronics packaging to biomaterials amongst others. Evolution of cure force and heat flow measured by means of DMA and DSC, respectively, at cure temperature 100 °C.

In the flip chip assembly process, no-flow underfill (NFU) has the advantage over traditional capillary-flow underfill because of the elimination of processing steps and the reduction of packaging cost. However, currently one of the major technical obstacles in applying no-flow underfill technology is the fillet cracking of no-flow underfill during the reflow after the moisture preconditioning. In this paper, comprehensive thermo-mechanical and hygroswelling models are established to study a larger die flip chip package with no flow underfill during reflow after moisture preconditioning. The adhesion strengths between no-flow underfill and die have been characterized. Based on the modelling results and the adhesion strength data, the reason why the crack on the no-flow underfill starts and propagates, leading to fillet cracking, is also explained. A series of parametric studies are also performed to eliminate or reduce the fillet crack. The results show that a lower coefficient of thermal expansion (CTE), a lower Young's modulus (E) and a higher cure temperature of no-flow underfill are desirable for the robustness of the package. The results also show that thinner die thickness is desirable for the robustness of the package. These findings form design guidelines for the design of larger die, copper pillar bump flip chip package with no-flow underfill.

PurposeThis paper aims to present a new micro‐impact tester developed for characterizing the impact properties of solder joints and micro‐structures at high‐strain rates, for the microelectronic industry, and the results evaluated for different solder ball materials, pad finishes and thermal histories by using this new tester. Knowledge of impact force is essential for quantifying the strength of the interconnection and allows quantitative design against failure. It also allows one‐to‐one comparison with the failure force measured in a standard quasi‐static shear test.Design/methodology/approachAn innovative micro‐impact head has been designed to precisely strike the specimen at high speed and the force and displacements are measured simultaneously and accurately during the impact, from which the failure energy may be calculated.FindingsThe paper demonstrates that, peak loads obtained from the impact tests are between 30 and 100 percent higher than those obtained from static shear tests for all combinations of solder alloy and pad finish. The SnPb solder alloy had the maximum energy to failure for all pad finishes. Of all the lead‐free solders, the SnAg solder alloy had the highest energy to failure. Static shearing induces only bulk solder failure for all combinations of solder alloy and pad finish. Impact testing tends to induce bulk solder failure for SnPb solder and a mixture of bulk and intermetallic failure in all the lead‐free solder alloys for all pad finishes. In general, the peak loads obtained for solder mask defined pads are significantly higher than those for non‐SMD (NSMD) pads. The results obtained so far have highlighted the vulnerability of NSMD pads to drop impact.Practical implicationsThe work provides a new solution to the microelectronics industry for characterizing the impact properties of materials and micro‐structures and provides an easy‐to‐use tool for research or process quality control.Originality/valueThe new micro‐impact tester developed is able to perform solder ball shear testing at high speeds, of up to 1,000 mm/s, and to obtain fracture characteristics similar to those found in drop impact testing using the JEDEC board level testing method JESD22‐B111 – but without the complexity of preparing specialized boards. This is not achievable using standard low‐speed shear testers.

The reaction kinetics of a commercial fast cure nonconductive adhesive has been systematically investigated using differential scanning calorimetry. Samples were isothermally cured at temperatures from 120 to 160/spl deg/C and dynamically cured at ramp rates between 5 and 20/spl deg/C/min. A good agreement between the autocatalytic kinetic model prediction and experimental results was demonstrated. Deviation occurred at high degrees of cure for curing below 140/spl deg/C due to the occurrence of vitrification. Additionally, by comparing the dynamic cure prediction with the isothermal experiment, good agreements and equivalence were demonstrated. As such, it is possible to predict the isothermal reaction behavior of fast cure materials at high temperature provided that the variation between the actual temperature of the heating system and the setting temperature is not large. Furthermore, the effect of curing process on the adhesion strength has been demonstrated by testing the shear strength of lap joint specimens. It was found that the evolution of adhesion strength was largely dependent on the buildup of mechanical properties during the curing process. At low and medium degrees of cure, cohesive and adhesive failures were respectively observed, while at high degrees of cure, adhesion strength surpassing the shear strength of the solder mask was observed. The sharp increase in adhesion strength was observed to coincide with the gelation point marked by the crossover between the storage and loss modulii, thus suggesting that the contributors to adhesion strength include mechanical interlocking as well as chemical bonding, as evidenced by buildup of storage modulus and mechanical strength of the adhesive.

Stress corrosion cracking and the associated time-dependent subcritical debonding of the underfill-die interface is believed to be responsible for a large disparity between the reliabilities of flip chip-underfill packages subjected to two different aging conditions: 1) 85/spl deg/C/85% RH (>3500 h) and 2) 121/spl deg/C/100% RH (/spl sim/100 h). The ratio of the transverse stress at the bump (Sy) to the shear stress at the die edge (Sxy) has been found to correlate well with the two characteristic autoclave failure signatures: random local failure and die edge delamination. The first failure mode is promoted by a high Sy-Sxy ratio. A practical finding from this study is that raising the curing temperature of the underfill offers a simple and effective means of enhancing the autoclave performance of the flip chip-underfill package.

Summary: We report a new methodology to determine the gelation and vitrification of a thermosetting material during the polymerization process by detecting the evolution of cure shrinkage through a thermomechanical analyzer (TMA) and a differential scanning calorimeter (DSC). The gelation and vitrification determined by the evolution of cure shrinkage correspond favorably with that measured by conventional rheological techniques. The isoconversional phenomenon at gelation point was further confirmed by monitoring cure shrinkage at temperatures ranging from 90 to 110 °C. Whereas, vitrification was observed to occur at higher degrees of cure with increasing cure temperatures. Inhibited cure shrinkage was also observed in the vitrification region where the reaction transitioned from chemical to diffusion controlled. Combination of dimension change detected by DMA and heat flow detected by DSC for determining the relationship of cure shrinkage and degree of cure.

Adhesive flip chip interconnect has been recognized as a promising substitute for solder interconnection due to its fine-pitch, lead-free, and low-temperature processing capabilities. As adhesives are made of polymers, moisture absorption by the polymeric resin remains as one of the principal contributors to adhesive joint failure mechanisms. In this research, the reliability performance of the adhesive flip chip in the pressure cooker test and moisture sensitivity test conditions was investigated. The failure modes were found to be interfacial delamination and bump/pad opening which may eventually lead to total loss of electrical contact. Different sizes of bump/pad opening in the interconnections were discussed in the context of the significance of mismatch in coefficient of moisture expansion (CME) between adhesive and other components in the package, which induces a hygroscopic swelling stress. The effect of moisture diffusion in the package and the CME mismatch were also evaluated from the standpoint of finite element modeling. In this study, it is concluded that hygroscopic swelling assisted by loss of adhesion strength upon moisture absorption is responsible for the moisture-induced failures in these adhesive flip chip interconnects.