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This report covers the second quarter, Phase II of a program on ion implanted planar GaAs (gallium arsenide) integrated circuit technology. The overall objective of this program is the development of a manufacturable process for high-speed low-power GaAs logic circuits. The goal for Phase I was to establish the technology, and demonstrate its viability by fabricating circuits reaching MSI complexity. The goal for Phase II is to achieve the capability of fabricating GaAs ICs of LSI complexity. The most important result in this quarter was the successful demonstration of an 8:1 data multiplexer and a 1:8 data demultiplexer operating at clock rates as high as 1.1 GHz. In addition, operation of 8 circuits has been observed at frequencies as high as 1.9 GHz. Thus, the design objective for the operating speed of these demonstration circuits has been achieved., Prepared in cooperation with Crystal Specialties, Inc., California Inst. of Technology and Cornell Univ.

In this report, the design, fabrication and evalaution of a high sensitivity 1.06 micrometers optical receiver is reported. This receiver utilizes a high-speed, high quantum efficiency III-V alloy heterojuction photodiode with very low junction capacitance (approx. 0.3 pf) hybrid integrated with a low-current noise transimpedance type preamplifier. The receiver is designed to operate in the 0-5 MHz band. These receivers have been shown to be the most sensitive wideband detectors of 1/06 micrometers radiation to date. The work reported here entailed several distinct (1) Liquid phase epitaxial growth of photodiode material, photodiode fabrication and evlauation. (2) Fabrication of extremely low capacitance feedback resist or (C or = 1 x 10 to the -15th power F). (3) Fabrication of receiver. (4) Development of measurement techniques and evaluation of receivers.

The design and progress towards realizing very high sensitivity 1.06 micrometers photodetectors are reported. This research program consists of two projects: a high sensitivity 5 MHz optical receiver and a field-assisted double heterojunction photocathode. A 5 MHz, 1.06 micrometers GaAsSb avalanche photodiode (APD) receiver was built, tested and its noise performance modeled to determine the ultimate performance achievable with this technology. The initial receiver was better than an equivalent Si APD receiver by a factor of 2, and this was with very low gain in the GaAsSb APD. Considerable overall improvement is predicted with higher gain APDs. Cs activation to achieve negative electron affinity (NEA) on heterojunction devices has been the major emphasis in the photocathode project. A sputter cleaning and annealing process was developed which produced excellent activations on GaAs. The first results are reported on a double heterojunction device which has been activated to NEA and operated in vacuum. This device exhibited very large dark current under applied bias which is not yet understood. Further work in understanding this dark current will be required in order to realize the potential of the field-assisted photocathode. (Author)

This report covers the first quarter, Phase II of a program on ion implanted planar GaAs integrated circuit technology. The overall objective of this program is the development of a manufacturable process for high-speed low- power GaAs logic circuits. The goal for Phase I was to establish the technology, and demonstrate its viability by fabricating circuits reaching MSI complexity. The goal for Phase II is to achieve the capability of fabricating GaAs ICs of LSI complexity. The program involves the Rockwell International Science Center and three subcontractors; Crystal Specialties Inc., California Institute of Technology and Cornell University. The most important result obtained in this quarter is the verification of proper operation of an 8-channel multiplexer. This multiplexer, employing 64 gates, is the most complex GaAs IC built to date. The first multiplexer results show operation at moderate speed, 254 MHz clock rate with low power dissipation, 80 mW, for the entire circuit. Testing of wafers which are expected to demonstrate operation at higher speed is in progress., Prepared in cooperation with Crystal Specialties Inc., California Inst. of Technology and Cornell Univ.