1. Defects evolution in Si-based laterally diffused metal oxide semiconductor chip under repetitive gate transmission line pulse stress.
- Author
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Li, Huiying, Zheng, Xinyuan, Ning, Yibo, Pan, Chengbing, Wang, Kai, and Zhao, Lixia
- Subjects
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METAL oxide semiconductors , *STRAY currents , *THRESHOLD voltage , *ELECTRIC lines , *ELECTRON capture , *ELECTRON traps - Abstract
The electrical properties and defects behavior in Si-based laterally diffused metal oxide semiconductor (LDMOS) chips under repetitive gate transmission line pulse stress were investigated. The results show that the threshold voltage increased by 22.4%, the output saturation current reduced by 12.5%, and the gate leakage current increased with the increasing gate voltage by 4.3 mA/V after the stress. An intrinsic trap H1 at 300 K was observed in the fresh Si-based LDMOS chip by using deep-level transient spectroscopy, where the activation energy did not change obviously, but the interface state density increased after the stress, resulting in the increase of threshold voltage. In addition, a new trap E1 appeared at 75 K in the stressed Si-based LDMOS chip, which may capture electrons, decreasing the effective electron concentration, leading to the decrease of the saturation current. High-resolution transmission electron microscopy results show that there are some cracks at the grain boundaries in poly-silicon, which may be the main path for the gate leakage current. Our study lays a foundation to further understand defects and their evolution in the Si-based LDMOS chips during the operation. [ABSTRACT FROM AUTHOR]
- Published
- 2025
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