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1. A 7nm CMOS technology platform for mobile and high performance compute application

Author

Dhruv Singh, A. Gassaria, V. Chauhan, A. da Silva, P. Lindo, Daniel J. Dechene, M. Gribelyuk, I. Ahsan, M. Hasan, Judson R. Holt, Rod Augur, Jaeger Daniel, G. Northrop, G. Gomba, Ghosh Somnath, H. Narisetty, Basanth Jagannathan, Ting-Hsiang Hung, P. Liu, Y. Zhong, T. Gordon, Y. Fan, C. Schiller, A. Blauberg, O. Patterson, B. Morganfeld, Andres Bryant, J. Choo, T. Nigam, B. Senapati, V. Sardesai, N. Baliga, C. An, I. Ramirez, Rishikesh Krishnan, Arkadiusz Malinowski, S. Lucarini, Z. Sun, Sadanand V. Deshpande, R. Bhelkar, Mahender Kumar, Kong Boon Yeap, D. Conklin, Q. Fang, R. Gauthier, Purushothaman Srinivasan, S. Crown, M. Ozbek, Linjun Cao, G. Han, Z. Song, L. Huang, C. Serrau, R. Sweeney, M. Tan, Keith Donegan, Souvick Mitra, A. Zainuddin, P. Agnello, Balasubramanian S. Haran, Haifeng Sheng, B. Greene, A. Hassan, Tabakman Keith, Xin Wang, Sanjay Parihar, L. Cheng, M. Lagus, Jessica Dechene, D. Xu, G. Gifford, M. Zhao, Jeyaraj Antony Johnson, Y. Yan, Rick Carter, Manoj Joshi, W. Kim, Gabriela Dilliway, Jack M. Higman, S. Kalaga, Kai Zhao, Jinping Liu, A. Ogino, M. Lipinski, Amanda L. Tessier, Garo Jacques Derderian, S. Madisetti, N. Shah, Christopher Ordonio, M. Aminpur, Rakesh Ranjan, S. Saudari, Christa Montgomery, Tony Tae-Hyoung Kim, Jeric Sarad, Jae Gon Lee, Bharat Krishnan, Joseph F. Shepard, L. Hu, J. Sporre, Akil K. Sutton, Eswar Ramanathan, Cathryn Christiansen, J.H. Han, J. Lemon, Patrick Justison, Natalia Borjemscaia, Scott C. Johnson, B. Cohen, Kan Zhang, Srikanth Samavedam, G. Xu, T. Xuan, Unoh Kwon, C. Meng, Katsunori Onishi, Y. Shi, C. Huang, R. Coleman, Manfred Eller, Shreesh Narasimha, B. Kannan, J. Yang, Vivek Joshi, W. Ma, Christopher D. Sheraw, A. K. M. Mahalingam, Craig Child, E. Woodard, Tao Chu, Y. Jin, D. K. Sohn, Hasan M. Nayfeh, Mary Claire Silvestre, M. Lingalugari, G. Biery, Tian Shen, Carl J. Radens, E. Kaste, C-H. Lin, K. Han, K. Anil, Ankur Arya, Mehta Jaladhi, Jia Zeng, S.L. Liew, Michael V. Aquilino, M. Yu, M. Chen, Rohit Pal, E. Maciejewski, Stephan Grunow, Robert Fox, and Rinus T. P. Lee

Subjects
010302 applied physics, Computer science, Extreme ultraviolet lithography, Process (computing), 02 engineering and technology, 021001 nanoscience & nanotechnology, Low voltage sram, 01 natural sciences, Capacitance, CMOS, Computer architecture, Logic gate, 0103 physical sciences, Leverage (statistics), 0210 nano-technology, Immersion lithography
Abstract

We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.

Published
2017

2. High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

Author

E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, and Dureseti Chidambarrao

Subjects
Engineering, Subthreshold conduction, business.industry, Processor design, Copper interconnect, Soi finfet, Hardware_PERFORMANCEANDRELIABILITY, Thread (computing), Planar, CMOS, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, business, Dram
Abstract

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

Published
2014

3. PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology

Author

Henry K. Utomo, T. Okawa, Deleep R. Nair, R. Divakaruni, Qintao Zhang, C. W. Lai, Liyang Song, Shin-Ae Lee, Emmanuel Josse, A. Pofelski, H. Onoda, Yue Liang, Chendong Zhu, X. Wu, William K. Henson, Christian Gruensfelder, Judson R. Holt, R.Q. Williams, Thomas A. Wallner, E. Kaste, Y. M. Lee, J.W. Weijtmans, Brian J. Greene, Melanie J. Sherony, and J. Brown

Subjects
Materials science, CMOS, business.industry, Logic gate, MOSFET, Electronic engineering, Optoelectronics, Edge (geometry), business, Stress strength, Capacitance
Abstract

The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap capacitance. This observation was confirmed by an eSiGe fill level study. Compared to PC-bounded eSiGe, STI-bounded devices have increase variation due to eSiGe process.

Published
2012

4. New layout dependency in high-k/Metal Gate MOSFETs

Author

R. Divakaruni, Jaeger Daniel, Richard A. Wachnik, N-S. Kim, M. Celik, Y. Takasu, J. Sudijono, S. Mori, Melanie J. Sherony, H. Nishimura, Michael P. Chudzik, K-C. Lee, Y-W. Teh, Liyang Song, Ricardo A. Donaton, J.-P. Han, E. Kaste, T. Iwamoto, Knut Stahrenberg, Vijay Narayanan, J. Liang, Fumiyoshi Matsuoka, Manfred Eller, S. Kohler, K. Kim, JiYeon Ku, Katsura Miyashita, M-H. Na, S. Johnson, Wai-kin Li, Jongpal Kim, H. V. Meer, Christophe Bernicot, Ron Sampson, Deleep R. Nair, Franck Arnaud, M. Sekine, W. Neumueller, S. Miyake, Masafumi Hamaguchi, Kathy Barla, J.H. Park, and H. Kothari

Subjects
Materials science, Reliability (semiconductor), Dependency (UML), Modulation, business.industry, MOSFET, Electronic engineering, Optoelectronics, Process optimization, Metal gate, business, Threshold voltage, High-κ dielectric
Abstract

We report a new N/PFET Gate Patterning Boundary Proximity layout dependent effect in high-k dielectric/Metal Gate (HK/MG) MOSFETs which causes anomalous threshold voltage (V t ) modulation for the first time. We investigated the mechanism by using special test structures and process optimizations to suppress this layout dependency. Finally, we achieved the best over all process optimization which makes it possible to suppress layout dependency without degrading FET performance/yield/reliability.

Published
2011

5. EPIDEMIOLOGY

Author

D. T. Nagasawa, M. Bergsneider, D. Kelly, B. Shafa, D. Duong, J. Ausman, L. Liau, D. McBride, I. Yang, B. S. Mann, R. Yabroff, L. Harlan, C. Zeruto, J. Abrams, V. Gondi, J. Eickhoff, W. A. Tome, K. R. Kozak, M. P. Mehta, K. M. Field, K. Drummond, M. Yilmaz, P. Gibbs, M. A. Rosenthal, R. Allaei, K. J. Johnson, A. J. Hooten, E. Kaste, J. A. Ross, D. A. Largaespada, D. R. Johnson, B. P. O'Neill, T. Rice, S. Zheng, Y. Xiao, P. A. Decker, L. S. McCoy, I. Smirnov, J. S. Patoka, H. M. Hansen, J. L. Wiemels, T. Tihan, M. D. Prados, S. M. Chang, M. S. Berger, A. Pico, A. Rynearson, J. Voss, A. Caron, M. L. Kosel, B. L. Fridley, D. H. Lachance, C. Giannini, J. K. Wiencke, R. B. Jenkins, M. R. Wrensch, J. C. Buckner, P. A. Burch, R. C. Thompson, L. B. Nabors, J. J. Olson, S. Brem, M. H. Madden, J. E. Browning, K. M. Egan, E. A. Pereira, J. Livermore, D. M. Alexe, R. Ma, O. Ansorge, T. A. Cadoux-Hudson, M. Wang, J. Dignam, M. Won, W. Curran, M. Mehta, M. Gilbert, A. R. Terry, F. G. Barker, L. R. Leffert, B. Bateman, I. Souter, S. R. Plotkin, O. Ishaq, J. Montgomery, S. Terezakis, M. Wharam, M. Lim, M. Holdhoff, L. Kleinberg, K. Redmond, C. Kruchko, A. M. Paker, T. L. Chi, C. Kamiya-Matsuoka, M. E. Loghin, T. Lautenschlaeger, V. Dedousi-Huebner, and A. Chakravarti

Subjects
Cancer Research, Abstracts, Oncology, Neurology (clinical)
Published
2011

6. Cost Efficient Novel High Performance Analog Devices Integrated with Advanced HKMG Scheme for 28nm CMOS Technology and Beyond

Author

Melanie J. Sherony, J. Liang, M. Voelker, Myung-Hee Na, Jaeger Daniel, Kathy Barla, Y. Goto, G. Yang, Katsura Miyashita, Frank Scott Johnson, J.H. Park, R. Sampson, Jenny Lian, Kenneth J. Stein, JiYeon Ku, Christophe Bernicot, Knut Stahrenberg, S. Miyake, J. Sudijono, Haoren Zhuang, Li-Hong Pan, Ricardo A. Donaton, Martin Ostermayr, Gen Tsutsui, Manfred Eller, Richard A. Wachnik, S. Kohler, K. Kim, Wai-kin Li, Christian Wiedholz, M. Celik, Atsushi Azuma, An L. Steegen, T. Shimizu, Anda Mocuta, J.-P. Han, E. Kaste, H. van Meer, Masafumi Hamaguchi, Deleep R. Nair, N-S. Kim, Franck Arnaud, W. Neumueller, and D. Chanemougame

Subjects
Scheme (programming language), Materials science, Cost efficiency, CMOS, Electronic engineering, computer, computer.programming_language
Published
2010

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