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CMP is a complex process that combines the synergistic effect of a chemical action performed by the slurry and a mechanical one done by the pad and the abrasive particles of the slurry. The pad plays a key role in the CMP process as it contributes to both chemical and mechanical actions. In this paper, we focused on the pad pores, which act on the two sides of the chemical/mechanical balance. Pads with different porosities were investigated. The effect of pad microstructure on CMP performance were studied. A 3D confocal microscope was used to analyze pad roughness parameters, height distributions and asperities properties. Silicon blanket wafers were polished using different pads and were then characterized in order to extract surface roughness, removal rate and defect level. The surface quality of the wafer post process presents a direct correlation with pad topography. A smaller pad pore size (i.e. smooth surface) shows a beneficial effect on the wafer roughness. We further discuss the effect of pore size on pad topography by studying asperities properties and volume available for slurry transportation. The consequences of pore characteristics are then correlated to CMP performance. This study allows us to understand how we can manage the chemical/mechanical actions through the pad microstructure.

Semiconductor devices become more complicated and the need for the use of semiconductor chips in portable products increases, the need for thinner chips and packages becomes greater. It brings great challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. In the meantime, high reliability remains a critical necessity. The silicon die strength can be adversely affected during various manufacturing processes, such as thinning and dicing. A realistic understanding of the die strength measurement significance is very important for process monitoring and package selection, and risk assessment in the early design stage. The three-point bending test was used to determine the die strength on several samples embedding different Front-End configurations from simple bare silicon up to a real CMOS product with brittle ULK BEOL stack and copper patterning. A 3D anisotropic model based on finite element simulation was developed to assess the relevance and the limitations of the measurement method. SEM analysis were introduced to support the discussion. It has been concluded the highest is the die strength, the smallest should be the sample supporting blade span. However intrinsically to the dicing method and the three-point bending test, the die strength value dispersion is consequently spread.

andGeTeoxidationontheirphase-changepropertieswerestudiedbyopticalmeasurementsandParallelAngleResolved X-ray Photoelectron Spectroscopy (PARXPS). The influence of oxygen on the active material was depicted in order toexplain variations of the phase-change properties. The surface analysis evidenced a two-steps oxidation involving the formation ofgermanium and antimony oxides then tellurium oxide. A smooth surface sputtering allowed physically distinguishing the differentoxidesonGeTesampleoverlayerandgaveinformationaboutoxidationmechanisms.Asignificantdriftofcrystallizationtemperaturesand activation energies were observed after 12 months air exposure time that points out the influence of the phase-change materialsoxidation on their active properties.©2012 The Electrochemical Society. [DOI: 10.1149/2.027204jes] All rights reserved.Manuscript submitted October 10, 2011; revised manuscript received January 1, 2012. Published January 19, 2012.

Phase-change memory is one of the most promising technologies for the future non-volatile memories generation and the synthesis of highly conformal active material is one of the main challenges. Herein, we report the successful chemical vapor deposition of phase change materials conducted using original plasma enhanced pulsed liquid injection system. Smooth, conformal and amorphous as well crystalline GeTe layers were grown on large surfaces. Their phase-change characteristics present fast switch from amorphous to crystalline phases with high optical contrast between the two states. These properties are similar to those of sputtered films used in electronic devices. Moreover, thanks to appropriate process tuning, material structure and phase change properties can be tuned.

The microstructure of thin HfO2–Al2O3 nanolaminate high κ dielectric stacks grown by atomic vapor deposition has been studied by attenuated total reflection spectroscopy (ATR) and 8 eV spectroscopic ellipsometry (SE). The presence of Al2O3 below HfO2 prevents the crystallisation of HfO2 if an appropriate thickness is used, which depends on the HfO2 thickness. A thicker Al2O3 is required for thicker HfO2 layers. If crystallisation does occur, we show that the HfO2 signature in both ATR and 8 eV SE spectra allows the detection of monoclinic crystallites embedded in an amorphous phase.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 µm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz f T and 370 GHz f MAX associated with a CML ring oscillator gate delay τ D of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

Recently Silicon Photonics has generated an outstanding interest for integrated optical communications. In this paper we describe a 300mm Silicon Photonics platform designed for 25Gb/s and above applications at the three typical communication wavelengths and compatible with 3D integration. Main process features and device results are described.

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.

Among all the new memories concepts, Phase Change Memories (PCM) is one of the most promising. However, various challenges remain. This paper reviews the materials and processes required to face these challenges. As an example, attention will be made on the effect of Phase change material composition on stability of the amorphous phase i.e. on the retention of the information. Additionally, it is showed how specific processes such as CVD or ALD can be developed in order to minimize the current required to amorphize the phase change material i.e. to reset the device. Finally, with the perspectives of the advanced integration nodes, experimental results on the effect of scaling on phase transformation are presented and discussed.

All these results show mainly the effectiveness of 45° rotated substrate enabling an increase of mobility performance for PMOS as compared to not rotated substrate. For NMOS devices, combined access resistance and mobility improvements explain the performance gain for rotated substrate.

In this paper, we compare the electrical properties of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FD-SOI) MOS devices for rotated and not rotated substrate with different gate lengths. We found a significant performance enhancement on FD-SOI PMOSFETs as expected, while keeping a good control of short channel effects. Surprisingly, to a lower extent, an improvement is also found for NMOS devices. We have also studied the carrier mobility degradation as a function of temperature and we point out the contribution of different mechanisms that reduce the mobility such as impurity Coulomb scattering, phonons and neutral defects as a function gate length. We find that there is no significant effect of rotated substrate on the mobility degradation. All these results are discussed and possible explanations are also given.

Phase change memory technology is considered as one of the most promising resistive memory solution. One issue, however, is the high electrical current required to reset the information. Indeed large energies are mandatory for amorphization of the crystalline phase change material. It has been demonstrated that energies can be highly decreased by reduction of the active volume and confinement of the phase change material. To do so, phase change materials deposition route with high filling capacity is needed. Atomic Layer Deposition (ALD) is well known for its high conformity. However, such a process is still a challenge for phase change materials such as Ge x Sb y Te z (GST). In this work, (i) ALD GST films are processed and characterized and (ii) realisation of phase change memory devices using ALD GST is demonstrated on 200mm wafers.

This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.

The commercialization of Phase-Change Memories (PCM), based on the well-known GST compound, have been recently started, tailored for consumer applications. Despite other excellent performances (i.e. low-power, scalability,…), data retention is assured up to 85°C, still limited for the automotive market segment. Alternative active material able to comply with the stringent requirements of automotive applications should possibly exhibit higher crystallization temperature (T C ) as well as higher Activation Energy (E A ) with respect to GST. Recent literature shows that GeTe provides better retention [1–3], while several works put in evidence how data retention is enhanced by inclusions in pure host alloys [4–6].

In this paper we present a study of Phase-Change non-volatile Memory (PCM) devices integrating carbon-doped GeTe as chalcogenide material. Carbon-doped GeTe, named GeTeC, remarkably lowers the RESET current and features very good data retention properties as well. In particular, GeTe PCM with 10% carbon inclusions (named GeTeC10%) yields about 30% of RESET current reduction with respect to pure GeTe and GST. Furthermore, our GeTeC10% memory cells are expected to guarantee a 10-years-lifetime-temperature of about 127°C, which is one of the highest ever reported for PCM. The outstanding properties of GeTeC make this material promising for non-volatile memory technologies.

This paper investigates material and electrical properties of a new chalcogenide alloy for Phase-Change Memories (PCM): Carbon-doped GeTe (named GeTeC). First, several physico-chemical, optical and electrical analyses have been performed on full-sheet chalcogenide depositions in order to understand the intrinsic GeTeC phase-change behavior, and to characterize structure and composition of amorphous and crystalline states. Then, GeTeC with two different Carbon doping (4% and 10%) has been integrated in pillar-type analytical PCM cells. Physico-chemical and electrical data indicate that GeTeC is characterized by a much more stable amorphous phase compared to undoped GeTe. Thus, GeTeC offers a slower programming speed versus GeTe, but an improved data retention at high temperature. Finally, we argue that GeTeC alloy is a promising candidate for future developments of PCM technologies for embedded applications.

100 nm-thick GeSbN films with high Sb content were investigated by XRD and TEM in order to investigate crystalline phases. We observe the crystallization of the two phases separatly. First, Sb rhomboedral crystallizes at 250°C and then cubic Ge appears at 340°C according to Reflectivity and X-Ray Diffraction measurements. With the incorporation of nitrogen in the thick films, a delay to crystallization of the two phases is observed. Grain size measurements with Scherrer formula support the decrease of grain crystallization with N content. Moreover, TEM observations show clearly the separation of the two phases in the layer and the reduction in size of the grains with nitrogen content. This allows a better re-amorphization than films without nitrogen.

International audience; Future integration of metal-insulator-metal capacitors requires devices with high capacitance density and low quadratic voltage coefficient of capacitance . A major problem is that the increase in capacitance density is usually accompanied by increased voltage nonlinearities. By combining two high-k materials with opposite , it is demonstrated that it is possible to obtain capacitors with both high capacitance density and minimal nonlinearity. A SrTiO3 /ZrO2 bilayer was used to elaborate capacitors displaying a voltage coefficient of −60 ppm/V2 associated with a density of 11.5 fF/ m2. These devices constitute excellent candidates for the next generation of metal-insulator-metal capacitors.

International audience; This work reports on the study of two HfO(2) metal-insulator-metal structures using two different bottom metal electrodes: Pt and TiN. Different spectroscopic techniques had been used for the physicochemical characterization in order to study the junction interface and determine the oxide thickness and crystallinity: parallel angle resolved x-ray spectroscopy, vacuum ultraviolet ellipsometry, and attenuated total reflectance. Electrical characteristics of the structures with different oxide thicknesses and an evaporated gold counterelectrode are shown. Best results for very thin HfO(2) films in terms of voltage linearity are obtained with the platinum electrodes. This is correlated with differences observed between the continuous conductivity when using Pt electrode instead of TiN electrode. (C) 2009 American Vacuum Society.

In situ annealing Raman scattering is used to evidence germanium postcrystallization in the crystalline phase of Ge-rich phase-change GeTe thin films. Both reflectivity and Raman scattering show that the crystallization temperature of the as-deposited amorphous phase increases with increasing Ge content going from Tc=180 °C (Ge0.5Te0.5) to 360 °C for Ge-rich Ge0.76Te0.24. The crystallized phase adopts the rhombohedral α-GeTe phase structure, and whatever the starting composition. For Ge-rich GeTe we observe a second characteristic temperature around 375 °C, which signs the crystallization of a precipitated cubic Ge phase and thus the presence of two distinct phases.

High quality MIM capacitors with improved capacitance density, low leakage currents and linear C(V) behaviour are the object of active research, with potential applications in CMOS, BICMOS and bipolar technologies as filters, analog to digital converters and related radio-frequency operating devices. Several high-k materials (Ta2O5, HfO2, Y2O3, Al2O3-HfTiO, HfON-SiO2) have been put on trial as possible candidates for SiO2 substitution which is required by the aggressive downscaling of electronic devices. Among those, HfO2- based materials seem to offer promising properties, combining a high chemical stability with Si and a high k value. However, HfO2 shows a strong ability to favour charge defects such as oxygen vacancies, which in turn affect the intrinsic properties of devices such as threshold voltage or leakage currents. These oxygen vacancies are actually thought to accumulate in the vicinity of the electrode, thus forming an oxidized interfacial layer and inducing a significant voltage linearity degradation of MIM capacitors.In this work, it will be shown that this oxide layer thickness can be strongly minimized by using appropriate bottom electrode material. Indeed, high work function materials can efficiently prevent oxygen vacancies charge stocking on their surface. Several MIM devices have been prepared based on HfO2, Al2O3 and SrTiO3 as dielectric materials, and TiN, WSi2.7 and Pt as bottom electrode material. All these devices have been fully characterized in terms of materials properties and electrical behaviour. These results have been analysed and show that a reduced dielectric thickness is preferred to achieve high capacitance density, but is also responsible for voltage linearity degradation. High work function electrode material can help improve this degraded linear behaviour, thanks to the formation of a reduced interfacial oxygen trap layer thickness. Leakage currents seem to be deeply correlated with the morphological state of the dielectric material, an amorphous state being obviously more efficient to prevent current pathways through grain boundaries.All these results will be presented in detail and discussed with regards to different models proposed in the literature to account for these data.

In situ transmission electron microscopy (TEM) observations were performed for a better understanding of the “melt quenched” GeTe crystallization mechanism. The evolution of the crystallite morphology observed during annealing shows a growth-dominated crystallization behavior. Scanning transmission electron microscopy—electron dispersive x-ray spectroscopy and high resolution electron microscopy experiments were also performed on cycled GeTe devices, showing that void formation is responsible for the cell failure after 107 cycles.