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An analytical model to describe the bias dependent series resistances R/sub S/ and R/sub D/ of LDD MOSFETs down to quarter micron and below is introduced. Comparing measurement and simulation results of CMOS ring oscillators it has been found that for low voltage applications (V/sub dd/=1 V) an incorrect description of R/sub S/ and R/sub D/ can cause a simulation error of up to 30% in the delay time of CMOS inverters.

This paper presents criteria for the onset of NQS effects derived from time transient device simulations and S-parameter measurements. For the first time it has been proved that e.g, a 10 /spl mu/m NMOS transistor can be described up to 27 MHz and a 0.2 /spl mu/m device up to 46 GHz by the quasistatic approach while the accuracy of the description of the inversion layer charge is still 99%.

A physics based compact model describing the fatigue behavior of ferroelectric capacitors has been developed. Fatigue is a gradual decrease of detectable polarization with increasing number of polarization cycles. This can be caused by trapped charges which pin dipoles near the interface to the electrode. In order to polarize those pinned dipoles they have to be separated from the trapped charges by a higher electrical force. This force has been described in our model by additional coercive voltages representing the different polarization response of the dipoles in the interface region in contrast to those in the inner region of the ferroelectric capacitor. Our model has been implemented into a common-used circuit simulator showing good agreement with measurements.

A dynamic model has been developed that is based on the Preisach approach for ferroelectric capacitors. It accounts for different switching reaction of the dipoles dependent on the applied voltage gradients. A method for extracting the necessary parameters by measuring the coercive voltage versus applied frequency is provided. The model was verified by testing capacitors of different geometries. Excellent agreement was achieved between our measurements and the corresponding circuit simulations. The simulation of a FeRAM-cell with our new dynamic model shows that the bit line signal decreases substantially with fast read/write times.

A new resistance model for lightly doped source/drain regions featuring a nonlinear gate voltage dependence has been implemented in the Bsim3 v3 model. This is achieved by separating the LDS(D) resistance into a voltage dependent accumulation and a spreading part.