Search

Low-power consumption is becoming a crucial concern that cannot be neglected in system-on-chip (SoC) designs. Low-power solutions help designers to provide a powerful methodology to analyze, estimate, and optimize today’s power concerns. Early estimation of power at a high level reduces the redesign cycle and turn-around time. Power dissipation is a function of input patterns and their characteristics. This paper describes a power estimation technique by using predefined statistical characteristics-based input patterns, which gives the average power dissipation of individual intellectual property (IP) blocks and interconnects/buses in an SoC system design. During the power estimation phase, the discrete water cycle algorithm is implemented to generate optimized input patterns. Then Monte-Carlo zero-delay simulation approach is used for each individual IP block and buses at a high level. Total system power is the simple addition of average powers of IP blocks and buses. In experiments of entire IP-based SoC system with buses, our modified macromodel gives an average error of 7.91%. Accuracy of the proposed model is improved as compared to our previous model. [ABSTRACT FROM AUTHOR]

Abstract: The above article, published online on 16 November 2017 in Wiley Online Library1, has been retracted by agreement between the Editor‐in‐Chief and John Wiley & Sons. The retraction has been agreed due to major overlap with an article submitted to the Journal of Circuits, Systems, and Computers and published on 7 July 20172. The author has been informed of this action. [ABSTRACT FROM AUTHOR]

Low-power consumption in three-dimensional integrated circuits (3D IC) design is becoming an important concern that cannot be neglected. The multiple layers/dies are stacked in 3D IC and communicate with each other through-silicon-vias (TSVs) to work as a single device in order to achieve high performance with minimum power dissipation. This paper demonstrates high-level power modeling approach for the power estimation of homogenous integration of Network-on-Chip (NoC)-based mesh architecture in 3D IC design. The preliminary experimental work of power model is divided into two major parts of the design. The first part estimates the power of NoC architecture on each stack separately and the second estimates the power dissipation of the uniformly distributed TSVs and input/output (I/O) pads. The model uses a linear function to estimate the average power dissipation. For an entire IC design, the average power is extracted by simple addition of all power estimation results of the model. The design is operated with multiple frequencies to find the most appropriate frequency to minimize power dissipation. In experiments, the average maximum error is estimated 18.03%. [ABSTRACT FROM AUTHOR]

Low power is becoming a more crucial performance metrics in system-on-chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation. This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm is implemented for the generation of sequences of input signals during the power estimation procedure. The genetic algorithm concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte Carlo zero-delay simulation is performed for individual IP core and bus at a high level. By the simple addition of these cores/buses, power is predicted by a novel macromodel function. The metamodeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In the experiments with the IP-based SoC system, the average error is estimated at 11.42%. [ABSTRACT FROM AUTHOR]