Search

A device (1) and a method for fabricating such a device is described. The device (1) comprises a device layer (4), a substrate (2) defining a substrate plane (3). A device layer plane (5) is defined on the side of the device layer (4) facing the substrate (2). The device also comprises a waveguide (7) for guiding an electromagnetic wave. The waveguide (7) is supported on the substrate (2) via a support structure (6) extending from the substrate (2) to the device layer (4). The ratio of the largest distance (D1), perpendicular to the substrate plane (3), between a free surface of the waveguide (7) facing the substrate and any solid material to the height (h) of the waveguide (7) is more than 6, i.e. D1/h \textgreater 6. The ratio of the distance (D2), perpendicular to the substrate plane (3), between the device layer plane (5) and the substrate plane (3) to the height (h) of the waveguide (7) is more than 6, i.e. D2/h \textgreater 6., Library Catalog: ESpacenetQC 20210113

Single nanowires have a broad range of applications in chemical and bio-sensing, photonics, and material science, but realizing individual nanowire devices in a scalable manner remains extremely challenging. This work presents a scalable and flexible method to realize single gold nanowire devices. We use conventional optical stepper lithography to generate notched beam structures, and crack lithography to obtain sub-20-nm-wide nanogaps at the notches, thereby obtaining a suitable shadow mask to define a single nanowire device. Then a gold evaporation step through the shadow mask forms the individual gold nanowires with positional and dimensional accuracy and with electrical contacts to probing pads., QC 20200310

Tunneling junctions are pairs of electrodes separated by gaps of a few nanometers that allow electrons to tunnel across the gap. Tunneling junctions are of great importance for applications such as label-free biomolecule sensing and single molecule electronics, but their fabrication remains difficult and laborious. In this paper, we present a simple 2-stage process for the fabrication of tunneling junctions consisting of electrode pairs made of gold (Au). This is achieved by combining a novel methodology for fabricating crack-defined Au nanowires at wafer-scale with a constant voltage, feedback-free electromigration procedure to form tunneling nanogaps free of debris., QC 20200310

Single nanowires (NWs) have a broad range of applications in nanoelectronics, nanomechanics, and nano photonics, but, to date, no technique can produce single sub 20 nm wide NWs with electrical connections in a scalable fashion. In this work, we combine conventional optical and crack lithographies to generate single NW devices with controllable and predictable dimensions and placement and with individual electrical contacts to the NWs. We demonstrate NWs made of gold, platinum, palladium, tungsten, tin, and metal oxides. We have used conventional i-line stepper lithography with a nominal resolution of 365 nm to define crack lithography structures in a shadow mask for large-scale manufacturing of sub-20 nm wide NWs, which is a 20-fold improvement over the resolution that is possible with the utilized stepper lithography. Overall, the proposed method represents an effective approach to generate single NW devices with useful applications in electrochemistry, photonics, and gas- and biosensing., QC 20190430

Break junctions provide tip-shaped contact electrodes that are fundamental components of nano and molecular electronics. However, the fabrication of break junctions remains notoriously time-consuming and difficult to parallelize. Here we demonstrate true parallel fabrication of gold break junctions featuring sub-3 nm gaps on the wafer-scale, by relying on a novel self-breaking mechanism based on controlled crack formation in notched bridge structures. We achieve fabrication densities as high as 7 million junctions per cm(2), with fabrication yields of around 7% for obtaining crack-defined break junctions with sub-3 nm gaps of fixed gap width that exhibit electron tunneling. We also form molecular junctions using dithiol-terminated oligo(phenylene ethynylene) (OPE3) to demonstrate the feasibility of our approach for electrical probing of molecules down to liquid helium temperatures. Our technology opens a whole new range of experimental opportunities for nano and molecular electronics applications, by enabling very large-scale fabrication of solid-state break junctions., QC 20180914

QC 20190624

The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics. A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide. However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices. The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices. Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps. The most promising approaches that could achieve a breakthrough in research and commercial applications are identified. Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes., QC 20190107

Nanogap electrodes consist of pairs of electrically conducting tips that exhibit nanoscale gaps. They are building blocks for a variety of applications in quantum electronics, nanophotonics, plasmonics, nanopore sequencing, molecular electronics, and molecular sensing. Crack-junctions (CJs) constitute a new class of nanogap electrodes that are formed by controlled fracture of suspended bridge structures fabricated in an electrically conducting thin film under residual tensile stress. Key advantages of the CJ methodology over alternative technologies are that CJs can be fabricated with wafer-scale processes, and that the width of each individual nanogap can be precisely controlled in a range from <2 to >100 nm. While the realization of CJs has been demonstrated in initial experiments, the impact of the different design parameters on the resulting CJs has not yet been studied. Here we investigate the influence of design parameters such as the dimensions and shape of the notches, the length of the electrode-bridge and the design of the anchors, on the formation and propagation of cracks and on the resulting features of the CJs. We verify that the design criteria yields accurate prediction of crack formation in electrode-bridges featuring a beam width of 280 nm and beam lengths ranging from 1 to 1.8 mu m. We further present design as well as experimental guidelines for the fabrication of CJs and propose an approach to initiate crack formation after release etching of the suspended electrode-bridge, thereby enabling the realization of CJs with pristine electrode surfaces., QC 20171117

We present a single-lithography Mach-Zehnder interferometer sensor circuit, with integrated low back-reflection input and output grating couplers. The low back-reflection is accomplished by a duty cycle apodization optimized for coupling light between single-mode silica fibers and the nanometric silicon-on-insulator (SOI) rib-waveguides. We discuss the design, fabrication, and characterization of the circuit. The apodization profile of the gratings is algorithmically generated using eigenmode expansion based simulations and the integrated waveguides, splitters, and combiners are designed using finite element simulations. The maximum simulated coupling efficiencies of the gratings are 70% and the multimode interference splitters and combiners have a footprint of only 19.2ￜ4.5 ￜm2. The devices are fabricated on an SOI wafer with a 220 nmdevice layer and 2 ￜm buried oxide, by a single electron beam lithography and plasma etching. We characterize the devices in the wavelength range from 1460-1580 nm and show a grating pass-band ripple of only 0.06 dB and grating coupling efficiency of 40% at 1530 nm. The integrated Mach-Zehnder interferometer has an extinction ratio of -18 dB at 1530 nm and between -13 and -19 dB over the whole 1460-1580 nm range., QC 20120612, Cell-Ring