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In this paper a comprehensive procedure for the analog modeling of Fractional-Order Elements (FOEs) is presented. Unlike most already proposed techniques, a standard approach from classical circuit theory is applied. It includes the realization of a system function by a mathematical approximation of the desired phase response, and the synthesis procedure for the realization of basic fractional-order (FO) one-port models as passive RC Cauer- and Foster-form canonical circuits. Based on the presented one-ports, simple realizations of two-port differentiator and integrator models are derived. Beside the description of the design procedure, illustrative examples, circuit diagrams, simulation results and practical realizations are presented.

A generalized structure that is capable of implementing power-law filters derived from 1st and 2nd-order mother filter functions is presented in this work. This is achieved thanks to the employment of Operational Transconductance Amplifiers (OTAs) as active elements, because of the electronic tuning capability of their transconductance parameter. Appropriate design examples are provided and the performance of the introduced structure is evaluated through simulation results using the Cadence Integrated Circuits (IC) design suite and Metal Oxide Semiconductor (MOS) transistors models available from the Austria Mikro Systeme (AMS) 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process.

In this paper a third-order band-pass (BP) filter with geometrically-symmetrical characteristic is presented, for the first time to the authors knowledge. This filter characteristic is only possible to be obtained by fractional-order (FO) filter design. The desired characteristic was Chebyshev 0.1dB pass-band ripple and with normalized bandwidth $\mathrm{B}=0.1$ . Starting from common fourth-order BP transfer function the design was performed numerically using the nonlinear trust-region-reflective, least square algorithm in Matlab. The resulting third-order BP filter approximates very well in the pass-band frequency region, while possessing fractional step in the stop band. The wanted BP transfer function is realized as cascade in two ways: biquads with integer order (IO) and biquads with FO. The obtained design parameters in the IO and FO realizations are compared. Approximation of the constant phase element by Foster I passive RC network is used in a Pspice analysis. That Pspice analysis in a frequency and a time domain are confirming the realizability and stability of the proposed filter, respectively.

In this paper we examine the influence of coupling to reduce the sensitivity to component tolerances in a CMOS-CCII realization of a fourth-order band-pass filter using two two-integrator biquads: cascaded and coupled. It is shown how the CCII non-idealities, causing lossy integrators, influence the coupled biquad design. With the example of a fourth-order 1MHz/100kHz band-pass filter, the design is tested with post-layout simulations with AMS 0.35-micron technology using Cadence. The analysis of the performance of both filters is done with Cadence. It is demonstrated that the coupled biquads, although having one more CCII and a resistor, have significantly lower sensitivity to component tolerances than the equivalent biquad cascade.

In this paper we propose a new, programmable, easy-tunable, current-mode general-purpose Biquad (C-GP-B), using second-generation current conveyors (CCIIs), based on the well-known direct form II, which, among other transfer functions, is also suitable to realize band-rejection (BR) or notch transfer function. It is convenient for elliptic transfer function realizations because it can realize finite transfer function zeroes. Since it has low sensitivity and grounded capacitors it is suitable for integrated circuit (IC) design. The new Biquad is then compared in sensitivity performance with other two CCII-based versions of biquadratic sections obtained by different approaches. Since all presented Biquads use CCIIs they operate in the current mode, and are therefore suitable to realize filter circuits operating at higher frequencies, consuming less power, and needing lower supply voltage. As an example, the design procedure, and the Monte Carlo sensitivity analysis using PSpice were performed for a fourth-order elliptic low-pass (LP) filter.

This paper presents the low-sensitivity realization of narrow band-pass analog active filters using second-generation current conveyors. It is known that filters using multiple-feedback structures have reduced sensitivities to passive component tolerances. It was shown that using the follow-the leader (FLF) topology, the sensitivity of current transfer function magnitude was reduced when compared to the common cascade topology (CAS). The sensitivity reduction happens in the current mode in the same way as in the voltage-mode. Besides sensitivity, the output thermal noise is also reduced using the FLF topology. As an example, the design procedure and the Monte Carlo sensitivity, as well as output thermal noise analysis using PSpice were performed for a 4th-order Butterworth narrow BP filter.