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16. Very low temperature epitaxy of group-IV semiconductors for use in FinFET, stacked nanowires and monolithic 3D integration

17. Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

19. Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

20. Comprehensive study of Ga activation in Si, SiGe and Ge with 5 × 10−10 Ω·cm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation

21. Defect evaluation in strain-relaxed Ge0.947Sn0.053 grown on (001) Si.

22. Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

23. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

24. Influence of Doping and Tunneling Interface Stoichiometry on n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki Diode Behavior

25. Field Effect and Strongly Localized Carriers in the Metal-Insulator Transition MaterialVO2

29. Material Studies on Si:C Epitaxial Films Grown by CVD

30. Evaluation of the Si0.8Ge0.2-on-Si Epitaxial Quality by Inline Surface Light Scattering: A Case Study on the Impact of Interfacial Oxygen

31. An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

32. Undoped and in-situ B doped GeSn epitaxial growth on Ge by atmospheric pressure-chemical vapor deposition

34. Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

35. Heteroepitaxy of III-V Compound Semiconductors on Silicon for Logic Applications: Selective Area Epitaxy in Shallow Trench Isolation Structures vs. Direct Epitaxy Mediated by Strain Relaxed Buffers

37. Towards the Monolithic Integration of III-V Compound Semiconductors on Si: Selective Area Growth in High Aspect Ratio Structures vs. Strain Relaxed Buffer-Mediated Epitaxy

38. GeSn channel nMOSFETs: Material potential and technological outlook

41. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

43. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology

44. Contact resistivity and Fermi-level pinning in n-type Ge contacts with epitaxial Si-passivation

45. Ge Chemical Vapor Deposition on GaAs for Low Resistivity Contacts

46. Record low contact resistivity to n-type Ge for CMOS and memory applications

50. Simulation of the post-implantation anneal for emitter profile optimization in high efficiency c-Si solar cells.

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