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Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Over the last several decades, several innovative lithographic approaches have been introduced in an effort to extend device roadmaps for both memory and logic devices. For many years, the emphasis was almost strictly on resolution, with the thought that at some point, conventional reduction optical lithography would be wavelength restricted. The thought process changed around ten years ago however, with the introduction of pitch splitting techniques such as self-aligned patterning and multiple uses of litho/etch (LE) processes. For dense lines, Self-Aligned Double Patterning (SADP) methods extended resolution to about 20nm (half pitch) and was followed by quad patterning processes (SAQP) that could reduce the half pitch to 10nm. Multiple litho/etch processes have already been applied create 20nm half pitch dense contact arrays. Although these pattern multiplication processes have enabled the industry to continue to aggressively scale devices, the methods come with a cost; both technical and financial. The technical price we pay for pitch splitting comes in the way of critical dimension control and additional overlay terms (pitch walking). Despite the precision of our newest deposition and etch processes, the additional process steps used to reduce pitch introduce these types of errors. Any technology (NIL and EUVL for example) that can deliver a single litho step process has the opportunity to deliver a simplified solution with better CD and overlay control. In this work, we review the key elements that go into determining NIL CoO and compare it to existing technology. Two examples are described in detail; sub-19nm half pitch lines and dense 20nm contact arrays. The assumptions used in the model are described, and projections for further reducing CoO are discussed, based on tool throughput, mask life and other key factors.

Nanoimprint lithography manufacturing utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Throughputs of 80 wph have been demonstrated, and mix and match overlay of 3.7nm 3 sigma has been achieved. The technology has already been successfully applied as a demonstration to the fabrication of advanced NAND Flash memory devices. A similar approach can also be applied however to remove topography on an existing wafer, thereby creating a planar surface on which to pattern. In this paper, a novel adaptive planarization process is presented that addresses the problems associated with planarization of varying pattern densities, even in the presence of pre-existing substrate topography. The process is called Inkjet-enabled Adaptive Planarization (IAP). The IAP process uses an inverse optimization scheme, built around a validated fluid mechanics-based forward model that takes the pre-existing substrate topography and pattern layout as inputs. It then generates an inkjet drop pattern with a material distribution that is correlated with the desired planarization film profile. This allows a contiguous film to be formed with the desired thickness variation to cater to the topography and any parasitic signatures caused by the pattern layout. In this work, it was demonstrated that planarization efficiencies of up to 99.5% could be achieved, thereby reducing an initial ~100nm wafer topography down to as little as 0.6nm.

Pattern transfer is critical to any lithographic technology, and plays a significant role in defining the critical features in a device layer. As both the memory and logic roadmaps continue to advance, greater importance is placed on the scheme used to do the etching. For many critical layers, a need has developed which requires a multilayer stack to be defined in order to perform the pattern transfer. There are many cases however, where this standard approach does not provide the best results in terms of critical dimension (CD) fidelity and CD uniformity. As an example, when defining a contact pattern, it may be advantageous to apply a bright field mask (in order to maximize the normalized inverse log slope (NILS)) over the more conventional dark field mask. The result of applying the bright field mask in combination with positive imaging resist is to define an array of pillar patterns, which then must be converted back to holes before etching the underlying dielectric material. There have been several publications on tone reversal that is introduced in the resist process itself, but often an etch transfer process is applied to reverse the pattern tone. The purpose of this paper is to describe the use of a three layer reverse tone process (RTP) that is capable of reversing the tone of every printed feature type. The process utilizes a resist pattern, a hardmask layer and an additional protection layer. The three layer approach overcomes issues encountered when using a single masking layer. Successful tone reversal was demonstrated both on 300mm wafers and imprint masks, including the largest features in the pattern, with dimensions as great as 60 microns. Initial in-field CD uniformity is promising. CDs shifted by about 2.6nm and no change was observed in either LER or LWR. Follow-up work is required to statistically qualify in-field CDU and also understand both across wafer uniformity and feature linearity.

Step and Flash Imprint Lithography (S-FIL^(R)) is a unique method that has been designed from the beginning to enable precise overlay for creating multi-level devices. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates (imprint masks). For device manufacturing, one of the major technical challenges remains the fabrication of full-field 1X templates with commercially viable write times. Recent progress in the writing of sub-40nm patterns using commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing technology for the sub-32nm node. Here we report the critical dimension (CD) uniformity and process latitude of dense 32nm patterns from templates written with variable shape beam pattern generators. Uniformity on the template and in the imprinted field was 3.22 and 3.45nm, [email protected] Process latitude during the writing of the template was improved by increasing both feature bias and exposure dose. As an example, the slopes for the 36 and 32nm features are approximately 0.30 and 0.25nm/@mC/cm^2, respectively, indicating a substantial process window for exposure dose.

Imprint lithography has been included on the ITRS lithography roadmap at the 32, 22, and 16nm nodes. Step and flash imprint lithography (S-FIL®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100-nm feature resolution without the significant expense of multielement, high quality projection optics, or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For device manufacturing, one of the major technical challenges remains the fabrication of full field 1X templates with commercially viable write times. Recent progress in the writing of sub-40-nm patterns using commercial variable shape e...

Optical lithography has been successful in achieving deep sub-wavelength images by the continuous improvement of lens systems, resists and the introduction of phase shift masks. One of the key challenges in attempting to pattern feature sizes less than 32nm is the ability to minimize feature roughness while maintaining acceptable process throughput. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Step and Flash Imprint Lithography is a step-and-repeat imprint process that has demonstrated excellent feature resolution. Since the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. In this paper, LWR was evaluated for several different templates. Feature sizes ranging from 20nm to 50nm were studied, and LWR was calculated from SEM images of the template, on imprinted wafers, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3@s), and independent of the processing step and feature size. A minimum LWR of 1.7nm was achieved, which is the required LWR for processing at the 32nm node.

Typically, the Step and Flash Imprint Lithography (S-FIL^T^M) process uses field-to-field drop dispensing of UV-curable liquids for step-and-repeat patterning. Several applications, including patterned magnetic media, photonic crystals, and wire grid polarizers, are better served by a process that allows high-throughput, full-wafer patterning of sub-100nm structures with modest alignment. Full-wafer imprinting requires a full-wafer template; however, creation of a wafer-scale imprint template with sub-100nm structures is not feasible with direct-writing approaches. This paper describes a practical methodology for creating wafer-scale templates suitable for full-wafer imprinting of sub-100nm structures. The wafer-scale template is replicated from a smaller area master template using the S-FIL step-and-repeat process. The pattern is repeated to accommodate the wafer substrate targeted for a particular application. The tone of the master template is maintained by employing an SFIL/R^T^M (reverse tone) pattern transfer process. To create the replicate template, the patterns are imprinted onto a fused silica wafer that has been coated with chromium and an organic transfer layer. A silicon-containing resist, Silspin^T^M, is spun on to planarize the organic monomer material. Following an etch back of the Silspin, the monomer and transfer layer are patterned using the Silspin as a hard mask. The Silspin and monomer stack then serves as a masking layer for the chromium and fused silica etches. The remaining monomer and chromium are then removed to create a conformal replicate template.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22nm nodes. Step and flash imprint lithography (S-FIL^(TM)) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. This paper addresses steps required to achieve resolution at or below 32nm. Gaussian-beam writers are now installed in mask shops and are being used to fabricate S-FIL templates. Although the throughput of these systems is low, they can nevertheless be applied towards applications such as unit process development and device prototyping. Resolution improvements were achieved by optimizing the ZEP520A resolution and exposure latitude. Key to the fabrication process was the introduction of thinner resist films and data biasing of the critical features. By employing a resist thickness of 70nm and by negatively biasing features as much as 18nm, 28nm half-pitch imprints were obtained. Further processing improvements show promise for achieving 20nm half-pitch features on a template.

High-resolution overlay is considered to be an important challenge for imprint lithography processes. A key advantage of Step and Flash(TM) Imprint Lithography (S-FIL(TM)) is that it uses low-pressures (

In order for Step and Flash Imprint Lithography (S-FIL) to be considered a viable printing technology to produce sub-100nm geometries, a reliable pattern transfer etch process needs to be established. Unlike optical lithography processes, imprinting features via S-FIL creates a residual layer of several hundred angstroms thick, which requires a break-through etch prior to etching the transfer layer. Of greater concern is the etch barrier used as the imaging layer for S-FIL technology. The incorporated silicon content is limited to approximately nine percent, and the formulation is geared toward achieving mechanical properties for the imprinting process. As a result, typical oxygen-based plasmas used for transferring more conventional bi-layer structures are not compatible with the current S-FIL resist stack. A reducing chemistry using ammonia (NH"3) plasma has been developed in providing a selective etch process for pattern transfer using S-FIL technology. The development of this NH"3-based process was a key enabler in the fabrication of the world's first surface acoustic wave filters patterned via S-FIL technology.

The escalating cost of next generation lithography (NGL) is driven in part by the need for complex sources and optics. The cost for a single NGL tool could soon exceed $50 million, a prohibitive amount for many companies. As a result, several research groups are looking at alternative, low-cost methods for printing sub-100 nm features. Many of these methods are limited in their ability to do precise overlay. In 1999, Willson and Sreenivasan developed step and flash imprint lithography (S-FIL™). The use of a quartz template opens up the potential for optical alignment of the wafer and template. This paper reviews several key aspects of the S-FIL process, including template, tool, ultraviolet (UV)-curable monomer, and pattern transfer. Two applications are also presented: contact holes and surface acoustic wave (SAW) filters.

If imprint lithography is to be considered as a viable method for fabricating high density silicon-based circuits, an infrastructure must be established that is capable of supplying users with 1X templates. It is critical, therefore, that tools are available that can expose, inspect, and repair these templates. The purpose of this work is to present initial step and flash imprint lithography template results using a shaped-beam system. A Leica SB350 MW was used to expose ZEP 7000 resist. The SB350 is a variable shaped-beam tool with 50 kV electron optics. A Motorola template pattern transfer process was used to obtain final images in the template. Trenches as small as 33 nm were resolved, as were 44 nm holes. Further improvements may be possible by increasing the operating voltage to 100 kV, and further increasing the e-beam system line edge acuity.

The goal of the SFIL development program is to enable patterning of sub-100 nm features at room temperature and with minimal applied pressure. We believe the use of low viscosity materials and photopolymerization chemistry will enable SFIL to achieve the throughput required for use in the microelectronics industry. Additionally, the rigid transparent imprint template used in SFIL enables a precision in overlay alignment that is difficult to achieve in other imprint schemes. Previous work demonstrated the ability to use SFIL to pattern over existing topography, to pattern on curved surfaces, and to produce working simple optical devices. Studies of defectivity have not revealed significant defect generation, and in fact have revealed no catastrophic defect propagation. Recent work has focused on improving etching processes used to amplify the aspect ratio of the polymer features. With this recent work we have demonstrated polymer-on-Si semi-dense lines smaller than 50 nm made with the SFIL process.

Extremely large-area roll-to-roll (R2R) manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. In order to achieve low-cost nanopatterning, it is imperative to move toward high-speed imprinting, less complex tools, near zero waste of consumables, and low-cost substrates. We have developed a roll-based J-FIL process and applied it to a technology demonstrator tool, the LithoFlex 100, to fabricate large-area flexible bilayer wire-grid polarizers (WGPs) and high-performance WGPs on rigid glass substrates. Extinction ratios of better than 10,000 are obtained for the glass-based WGPs. Two simulation packages are also employed to understand the effects of pitch, aluminum thickness, and pattern defectivity on the optical performance of the WGP devices. It is determined that the WGPs can be influenced by both clear and opaque defects in the gratings; however, the defect densities are relaxed relative to the requirements of a high-density semiconductor device.

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry’s transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

The ability to pattern materials at the nanoscale can enable a variety of applications ranging from high density data storage, displays, photonic devices and CMOS integrated circuits to emerging applications in the biomedical and energy sectors. These applications require varying levels of pattern control, short and long range order, and have varying cost tolerances. Extremely large area roll to roll (R2R) manufacturing on flexible substrates is ubiquitous for applications such as paper and plastic processing. It combines the benefits of high speed and inexpensive substrates to deliver a commodity product at low cost. The challenge is to extend this approach to the realm of nanopatterning and realize similar benefits. The cost of manufacturing is typically driven by speed (or throughput), tool complexity, cost of consumables (materials used, mold or master cost, etc.), substrate cost, and the downstream processing required (annealing, deposition, etching, etc.). In order to achieve low cost nanopatterning, it is imperative to move towards high speed imprinting, less complex tools, near zero waste of consumables and low cost substrates. The Jet and Flash Imprint Lithography (J-FIL TM ) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. In this paper we have developed a roll based J-FIL process and applied it to technology demonstrator tool, the LithoFlex 100, to fabricate large area flexible bilayer wire grid polarizers (WGP) and high performance WGPs on rigid glass substrates. Extinction ratios of better than 10000 were obtained for the glass-based WGPs. Two simulation packages were also employed to understand the effects of pitch, aluminum thickness and pattern defectivity on the optical performance of the WGP devices. It was determined that the WGPs can be influenced by both clear and opaque defects in the gratings, however the defect densities are relaxed relative to the requirements of a high density semiconductor device.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. In previous studies, we have focused on defects such as random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. In this work, we attempted to identify the critical imprint defect types using a mask with NAND Flash-like patterns at dimensions as small as 26nm. The two key defect types identified were line break defects induced by small particulates and airborne contaminants which result in local adhesion failure. After identification, the root cause of the defect was determined, and corrective measures were taken to either eliminate or reduce the defect source. As a result, we have been able to reduce defectivity levels by more than three orders of magnitude in only 12 months and are now achieving defectivity adders as small as 2 adders per lot of wafers.

The use of bit pattern media beyond densities of 1Tb/in2 requires the ability to pattern dimensions to sub 10nm. This paper describes the techniques used to reach these dimensions with imprint lithography and avoid such challenges as pattern collapse, by developing improved resist materials with higher strength, and utilizing a reverse tone J-FIL/R process.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10 4 - 10 5 imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and the semiconductor mask replication process. A Perfecta TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.

The Jet and Flash Imprint Lithography (J-FIL ® ) process uses drop dispensing of UV curable resists for high resolution patterning. Several applications, including patterned media, are better, and more economically served by a full substrate patterning process since the alignment requirements are minimal. Patterned media is particularly challenging because of the aggressive feature sizes necessary to achieve storage densities required for manufacturing beyond the current technology of perpendicular recording. In this paper, the key process steps for the application of J-FIL to pattern media fabrication are reviewed with special atte ntion to substrate cleaning, vapor adhesion of the adhesion layer and imprint performance at >300 disk per hour. Also discussed are recent results for imprinting discrete track patterns at half pitches of 24nm and bit patterned media patterns at densities of 1 Tb/in 2 . Keywords: Imprint lithography, template, discrete track recording, bit pattern media, adhesion promoter, J-FIL, Jet and Flash imprint lithography

Defectivity has been historically identified as a leading technical roadblock to the implementation of nanoimprint lithography for semiconductor high volume manufacturing. The lack of confidence in nanoimprint's ability to meet defect requirements originates in part from the industry's past experiences with 1 × lithography and the shortage in enduser generated defect data. SEMATECH has therefore initiated a defect assessment aimed at addressing these concerns. The goal is to determine whether nanoimprint, specifically Jet and Flash Imprint Lithography from Molecular Imprints, is capable of meeting semiconductor industry defect requirements. At this time, several cycles of learning have been completed in SEMATECH's defect assessment, with promising results. J-FIL process random defectivity of < 0.1 def/cm2 has been demonstrated using a 120nm half-pitch template, providing proof of concept that a low defect nanoimprint process is possible. Template defectivity has also improved significantly as shown by a pre-production grade template at 80nm pitch. Cycles of learning continue on feature sizes down to 22nm. © 2011 SPIE.

The Jet and Flash Imprint Lithography (J-FIL TM ) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10 4 - 10 5 imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and processes specifically for semiconductor applications. The requirements needed for semiconductors dictate the need for a well defined form factor for both master and replica masks which is also compatible with the existing mask infrastructure established for the 6025 semi standard, 6" x 6" x 0.25" photomasks. Complying with this standard provides the necessary tooling needed for mask fabrication processes, cleaning, metrology, and inspection. The replica form factor has additional features specific to imprinting such as a pre-patterned mesa. A Perfecta TM MR5000 mask replication tool has been developed specifically to pattern replica masks from an e-beam written master. The system specifications include a throughput of four replicas per hour with an added image placement component of 5nm, 3sigma and a critical dimension uniformity error of less than 1nm, 3sigma. A new process has been developed to fabricate replicas with high contrast alignment marks so that designs for imprint can fit within current device layouts and maximize the usable printed area on the wafer. Initial performance results of this marks are comparable to the baseline fused silica align marks.

The Jet and Flash Imprint Lithography (J-FIL TM ) 1-7 process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 10 4 - 10 5 imprints. This suggests that tens of thousands of templates/masks will be required. It is not feasible to employ electronbeam patterning directly to deliver these volumes. Instead, a "master" template - created by directly patterning with an electron-beam tool - will be replicated many times with an imprint lithography tool to produce the required supply of "working" templates/masks. In this paper, we review the development of the pattern transfer process for both template and mask replicas. Pattern transfer of resolutions down to 25nm has been demonstrated for bit patterned media replication. In addition, final resolution on a semiconductor mask of 28nm has been confirmed. The early results on both etch depth and CD uniformity are promising, but more extensive work is required to characterize the pattern transfer process.

Imprint lithography has been shown to be an effective technique for the replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require a demonstration of defect levels commensurate with cost-effective device production. This work summarizes the results of defect inspections of hard disks patterned using Jet and Flash Imprint Lithography (J-FIL TM ). Inspections were performed with optical based automated inspection tools. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity and scattered light. Defects that have been identified in this manner are further characterized according to the morphology. The imprint process was tested after optimizing both the disk cleaning and adhesion layers processes that precede imprinting. An extended imprint run was performed and both the defect types and trends are reported.

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology

We used electron beam (e-beam) inspection (EBI) systems to inspect nano imprint lithography (NIL) resist wafers with programmed defects. EBI with 10nm pixel sizes has been demonstrated and capability of capturing program defects sized as small as 4nm has been proven. Repeating defects have been captured by the EBI in multiple die inspections to identify the possible mask defects. This study demonstrated the feasibility of EBI as the NIL defect inspection solution of 32nm and beyond.

The ever-growing demand for hard drives with greater storage density has motivated a technology shift from continuous magnetic media to patterned media hard disks, which are expected to be implemented in future generations of hard disk drives to provide data storage at densities exceeding 1012 bits per square inch. Jet and Flash Imprint Lithography (J-FILTM) technology has been employed to pattern the hard disk substrates. This paper discusses the infrastructure required to enable J-FIL in high-volume manufacturing; namely, fabrication of master templates, template replication, high-volume imprinting with precisely controlled residual layers, dual-sided imprinting and defect inspection. Imprinting of disks is demonstrated with substrate throughput currently as high as 180 disks/hour (dual-sided). These processes are applied to patterning hard disk substrates with both discrete tracks and bit-patterned designs.

Step and Flash Imprint involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the progress made in inspection and repair of 1X imprint masks A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. These defects were then inspected using three different electron beam inspection systems. Defect sizes as small as 8 nm were detected, and detection limits were found to be a function of defect type. Both subtractive and additive repairs were attempted on SRAM Metal 1 cells. Repairs as small as 32nm were demonstrated, and the repair process was successfully tested for several hundreds of imprints.

The ever-growing demand for hard drives with greater storage density has motivated a technology shift from continuous magnetic media to patterned media hard disks, which are expected to be implemented in future generations of hard disk drives to provide data storage at densities exceeding 1012 bits per square inch. Step and Flash Imprint Lithography (S-FIL) technology has been employed to pattern the hard disk substrates. This paper discusses the infrastructure required to enable S-FIL in high-volume manufacturing; namely, fabrication of master templates, template replication, high-volume imprinting with precisely controlled residual layers, and dual-sided imprinting. Imprinting of disks is demonstrated with substrate throughput currently as high as 180 disks/hour (dualsided). These processes are applied to patterning hard disk substrates with both discrete tracks and bit-patterned designs.

Step-and-Flash Imprint Lithography (S-FIL) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub 40nm CD lithography methods, the resulting high resolution, high throughput through clustering, 3D patterning capability, low process complexity, and low cost of ownership (CoO) of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high volume manufacturing requirements. In this paper we have presented various methods of residual (cross-linked) resist removal and final imprint mask cleaning demonstrated on the HamaTech MaskTrack automated mask cleaning system. Conventional and non-conventional (acid free) methods of particle removal have been compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

Step and Flash Imprint Lithography redefines nanoimprinting. This novel technique involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the limitations of inspection at half pitches of 32 nm and below. A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. Defects in both the mask and imprinted wafers were characterized scanning electron microscopy and the measured defect areas were calculated. These defects were then inspected using a KLA-T eS35 electron beam wafer inspection system. Defect sizes as small as 12 nm were detected, and detection limits were found to be a function of defect type.

Step and Flash Imprint Lithography redefines nanoimprinting. This novel technique involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is to understand the limitations of inspection at half pitches of 32 nm and below. A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1 cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in increments of 4 nm. Defects in both the mask and imprinted wafers were characterized scanning electron microscopy and the measured defect areas were calculated. These defects were then inspected using a KLA-T eS35 electron beam wafer inspection system. Defect sizes as small as 12 nm were detected, and detection limits were found to be a function of defect type.

Two essential process steps of the template fabrication chain are inspection and repair. The widely introduced gas assisted e-beam etching and deposition technique for mask repair offers crucial advantages, especially regarding the resolution capability. We started the evaluation of a new e-beam repair test stand based on the Zeiss MeRiT technology for UV-NIL template repair. For this purpose, templates with programmed defects of different shapes and sizes have been designed and fabricated. The repair experiments were focused on the development of recipes for quartz etching and deposition specifically tailored for NIL repair requirements Both, clear and opaque programmed defects have been repaired and the results have been analyzed. After recipe optimization, templates with repaired programmed defects have been imprinted on a Molecular Imprints Imprio 250 tool. By comparing template and imprint results we investigated the repair capability.

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32, 22 and 16 nm nodes. Step and Flash Imprint Lithography (S-FIL ®) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates. For sub-32 nm device manufacturing, one of the major technical challenges remains the fabrication of full-field 1x templates with commercially viable write times. Recent progress in the writing of sub-40 nm patterns using commercial variable shape e-beam tools and non-chemically amplified resists has demonstrated a very promising route to realizing these objectives, and in doing so, has considerably strengthened imprint lithography as a competitive manufacturing technology for the sub 32nm node. Here we report the first imprinting results from sub-40 nm full-field patterns, using Samsung's current flash memory production device design. The fabrication of the template is discussed and the resulting critical dimension control and uniformity are discussed, along with image placement results. The imprinting results are described in terms of CD uniformity, etch results, and overlay.

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3σ), and independent of the processing step and feature size.

Imprint lithography achieves high resolution patterning with low roughness by avoiding the tradeoff between pattern quality and process throughput - a tradeoff that limits the capability of photolithography with chemically amplified resists. This work demonstrates the use of ZEP520A electron-beam resist for fabrication of imprint masks (templates). It is shown that high resolution, low roughness patterns can be robustly transferred from imprint mask to imprint resist, and from imprint resist through etch transfer into the underlying substrate. Through improvements to the electron-beam patterning process, 22 nm half-pitch patterns are routinely achieved with linewidth roughness (LWR) of just 2.6 nm, 3σ

Critical to the success of imprint lithography and Step and Flash Imprint Lithography (S-FIL ® ) in particular is the manufacturing 1X templates. Several commercial mask shops now accept orders for 1X templates. Recently, there have been several publications addressing the fabrication of templates with 32nm and sub 32nm half pitch dimensions using high resolution Gaussian beam pattern generators. Currently, these systems are very useful for unit process development and device prototyping. In this paper, we address the progress made towards full field templates suitable for the fabrication of CMOS circuits. The starting photoplate consisted of a Cr hard mask (≤ 15nm) followed by a thin imaging layer of ZEP 520A. The EBM-5000 and the EBM-6000 variable shape beam pattern generators from NuFlare Technology were used to pattern the images on the substrates. Several key specifications of the EBM-6000, resulting in improved performance over the EBM-5000 include higher current density (70 A/cm 2 ), astigmatism correction in the subfields, optimized variable stage speed control, and improved data handling to increase the maximum shot count limitation. To fabricate the template, the patterned resist serves as an etch mask for the thin Cr film. The Cr, in turn, is used as an etch block for the fused silica. A mesa is formed by etching the non-active areas using a wet buffered oxide etch (BOE) solution. The final step in the template process is a dice and polish step used to separate the plate into four distinct templates. Key steps in the fabrication process include the imaging and pattern processes. ZEP520A was chosen as the e-beam resist for its ability to resolve high resolution images. This paper documents the resolution and image placement capability with the processes described above. Although ZEP520A is slow relative to chemically amplified e-beam resists, it is only necessary to pattern 1/16 th the area relative to a 4X reduction mask. Write time calculations for 1X templates have also been performed, and are compared to 4X photomasks.

A 3D template fabrication process has been developed, which enables the generation of high resolution, high aspect pillars on top of lines. These templates will be used to print both vias and metal lines at once for the dual damascene technology. Due to the complexity of state of the art CMOS designs only a variable shape e-beam (VSB) writer combined with chemically amplified resists (CAR) can be considered for the patterning process. We focused our work especially on the generation of high aspect pillars with a diameter below 50nm and the development of suitable overlay strategies for getting a precise alignment between the two template tiers. In this context we investigated the influence of exposure strategies on the overlay result across the entire imprint area of 25mm × 25mm. Finally, we realized templates according to the MII standard with different test designs and confirmed printability of one of them on a MII tool.

NIL technique enables an easy replication of three dimensional patterns. Combined with a UV printable low-k material the NIL lithography can dramatically simplify the dual damascene process. Goal of this work was to develop a template process scheme which enables the generation of high resolution pillars on top of corresponding lines for direct printing of later vias and metal lines. The process flow is based on conventional 6025 photomask blanks. Exposure was done on a variable shaped e-beam writer Vistec SB350 using a sample of an advanced negative tone CAR and Fujifilm pCAR FEP171 for the first and the second layer, respectively. Chrome and quartz etching was accomplished in an Oerlikon mask etcher Gen III and Gen IV. Assessment of the developed template process was done in terms of overlay accuracy, feature profile and resolution capability depending on aspect ratio and line duty cycle. Finally the printability of 3D templates fabricated according the developed process scheme was proved.

The Step and Flash Imprint Lithography (S-FIL TM ) process uses field-to-field drop dispensing of UV curable liquids for step and repeat patterning for applications where high-resolution mix-and-match overlay is desired. Several applications, including patterned media, photonic crystals and wire grid polarizers, are better served by a patterning process that prints the full wafer since alignment requirements are not so stringent. In this paper, a methodology for creating high resolution thin templates for full wafer (or disk) imprinting is described. The methods have been applied toward the imprinting of both photonic crystal and patterned media devices using a large area printing tool developed around the S-FIL process. Keywords: imprint, lithography, template, emerging market, photonic crystal, patterned media 1. INTRODUCTION Step and Flash Imprint Lithography (S-FIL TM ) is a unique method for printing sub-100 nm geometries. 1-3 When high-resolution alignment is needed, the S-FIL process uses field-to-field drop dispensing of UV curable liquids for step and repeat patterning. Several applications, including patterned media, photonic crystals and wire grid polarizers, are better served by a full substrate patterning process since the alignment requirements are minimal. In general, the substrates employed in these markets do not have the stringent flatness specifications needed for silicon integrated circuit fabrication. As a result the imprinting of nano-scale features becomes particularly challenging, especially when imprinting with thick templates. The lithographic requirements to image both photonic crystal and patterned media devices are extremely challenging. Each application presents unique problems for a more conventional optical projection approach. Photonic crystals, with periods comparable to the optical wavelength within a light emitting diode (LED), employ diffractive effects to couple out light that is otherwise unavailable, enhancing the overall efficiency of the LED. Photonic crystals can improve the efficiency of LEDs through two different mechanisms: improvement of the radiative efficiency of the device and im provement of the extraction efficiency.