246 results on '"Doug Burger"'
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2. With Shared Microexponents, A Little Shifting Goes a Long Way.
3. Shared Microexponents: A Little Shifting Goes a Long Way.
4. Microscaling Data Formats for Deep Learning.
5. Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic.
6. A Configurable Cloud-Scale DNN Processor for Real-Time AI.
7. Azure Accelerated Networking: SmartNICs in the Public Cloud.
8. Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point.
9. Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor.
10. Serving DNNs in Real Time at Datacenter Scale with Project Brainwave.
11. A cloud-scale acceleration architecture.
12. Configurable Clouds.
13. PocketTrend: Timely Identification and Delivery of Trending Search Content to Mobile Users.
14. A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs.
15. Priority-based cache allocation in throughput processors.
16. Mixed-Signal Charge-Domain Acceleration of Deep Neural networks through Interleaved Bit-Partitioned Arithmetic.
17. A reconfigurable fabric for accelerating large-scale datacenter services.
18. Dynamic-vector execution on a general purpose EDGE chip multiprocessor.
19. A reconfigurable fabric for accelerating large-scale datacenter services.
20. General-purpose code acceleration with limited-precision analog computation.
21. A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer.
22. EVX: Vector execution on low power EDGE cores.
23. How to implement effective prediction and forwarding for fusable dynamic multicore architectures.
24. Using managed runtime systems to tolerate holes in wearable memories.
25. Architecture support for disciplined approximate programming.
26. Neural Acceleration for General-Purpose Approximate Programs.
27. Exploiting microarchitectural redundancy for defect tolerance.
28. Pocket cloudlets.
29. Preventing PCM banks from seizing too much power.
30. Dark silicon and the end of multicore scaling.
31. The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors.
32. Exploiting criticality to reduce bottlenecks in distributed uniprocessors.
33. Dynamically replicated memory: building reliable systems from nanoscale resistive memories.
34. Use ECP, not ECC, for hard failures in resistive memories.
35. Using dead blocks as a virtual victim cache.
36. Evolving Compiler Heuristics to Manage Communication and Contention.
37. A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services.
38. Neural acceleration for general-purpose approximate programs.
39. An evaluation of the TRIPS computer system.
40. End-to-end validation of architectural power models.
41. Architecting phase change memory as a scalable dram alternative.
42. Better I/O through byte-addressable, persistent memory.
43. Analysis of the TRIPS prototype block predictor.
44. Composable Multicore Chips.
45. High performance dense linear algebra on a spatially distributed processor.
46. Strategies for mapping dataflow blocks to distributed hardware.
47. Low-power, high-performance analog neural branch prediction.
48. Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.
49. Counting Dependence Predictors.
50. Feature selection and policy optimization for distributed instruction placement using reinforcement learning.
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