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In this paper, we present a single silicon synaptic device that enables stochastic binary spike-timing-dependent plasticity. The single silicon synaptic device, which is similar to a conventional metal-oxide-semiconductor field-effect transistor structure, is implemented using standard complementary metal-oxide-semiconductor technology. The stochastic nature of the feedback mechanism induced by weak impact ionization is experimentally demonstrated. Because of probabilistic dynamics in the feedback mechanism, the single silicon synaptic device features stochastic binary spike-timing-dependent plasticity.

In this study, we examine the electrical characteristics of p+–n+–i–n+ silicon-nanowire field-effect transistors with partially gated channels. The silicon-nanowire field-effect transistors operate with barrier height modulation through positive feedback loops of charge carriers triggered by impact ionization. Our field-effect transistors exhibit outstanding switching characteristics, with an on current of ˜10−4 A, an on/off current ratio of ˜106, and a point subthreshold swing of ˜23 mV/dec. Moreover, the devices inhibit ambipolar characteristics because of the use of the partially gated structure and feature the p-channel operation mode.

In this work, we report a fully CMOS-compatible single silicon neuron device, by exploiting interlinked positive and negative feedback loops. The neuron device exhibits the key features of leaky integrate-and-fire functionality and can produce neuronal oscillations that resemble biological oscillations. The stochastic nature and analog input-sensitivity of the feedback switching dynamics are observed in the device. Moreover, the neuronal oscillations of the two-terminal device do not require any power supplied by external bias lines.

In this article, we present a transposable three-transistor static random access memory (3T-SRAM) array consisting of independent double-gate feedback field-effect transistors as binary synaptic devices and access transistors. The synaptic functions of the ${2} \times {2}$ SRAM array are investigated through mixed-mode technology computer-aided design simulations. This 3T-SRAM array provides parallel and bidirectional synaptic updates with fast operating speed. Furthermore, a simplified spike-timing-dependent plasticity learning rule is implemented by adjusting the widths of memory pulses. A compact cell area and a low-leakage power consumption allow this 3T-SRAM array to be used for adaptive synaptic devices in a large-scale neuromorphic system.

We present polarity control of the carrier injection for a feedback field-effect transistor (FBFET) with a selectively thinned p+-i-n+ Si nanowire (SiNW) channel and two separate gates. The SiNW FBFET can be reconfigured in the p- or n-channel operation modes via simple control of electric signals. The two separate gates induce potential barriers in the SiNW channel for selective control of the carrier injection. In contrast to previously reported reconfigurable transistors, our transistor features symmetry of the electrical characteristics for the p- and n-channel operation modes. Positive-feedback operation of the SiNW FBFET provides superior switching characteristics for the p- and n-type configurations, including the on/off ratios (∼ 105) and subthreshold swings (1.36-1.78 mV/dec). This novel transistor is a promising candidate for reconfigurable electronics.

We demonstrate the nonvolatile and volatile memory characteristics of a gate-all-around silicon nanowire feedback field-effect transistor (FBFET) with a nitride charge-storage layer analyzed by a commercial TCAD simulator. Our FBFET exhibits a threshold voltage window of 0.76 V with a programming/erasing time of ${1}~\mu \text{s}$ in the nonvolatile memory mode. We investigated the delay of read operations with accumulated charges in the intrinsic channel region in this memory mode. Moreover, the FBFET exhibits a sensing margin of 6.3 $\mu \text{A}$ and a read/write speed of 10 ns with an outstanding retention time, as well as nondestructive read characteristics in the volatile memory mode, allowing this device to operate without any refresh operation. In addition, we describe the operating principle of our device and demonstrate its potential as integrated memory for 3-D integrations.

In this study, we examine the electrical characteristics of

In this paper, we propose the design optimization of underlapped Si1–xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I–V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1–xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

In this study, we perform reconfigurable n- and p-channel operations of a tri-top-gate field-effect transistor (FET) made of a p+-i-n+ silicon nanowire (SiNW). In the reconfigurable FET (RFET), two polarity gates and one control gate induce virtual electrostatic doping in the SiNW channel. The polarity gates are electrically connected to each other and program the channel type, while the control gate modulates the flow of charge carriers in the SiNW channel. The SiNW RFET features simple device design, symmetrical electrical characteristics in the n- and p-channel operation modes using p+-i-n+ diode characteristics, and both operation modes exhibit high ON/OFF ratios (∼106) and high ON currents (∼1 μA μm−1). The proposed device is demonstrated experimentally using a fully CMOS-compatible top-down processes.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications.

In this study, we propose complementary metal-oxide−semiconductor (CMOS) NOR logic gates consisting of silicon nanowire (NW) arrays on bendable substrates. A circuit consisting of two p-channel NW field-effect transistors (NWFETs) in series and two n-channel NWFETs in parallel is constructed to operate a two-input CMOS NOR logic gate. The NOR logic gates operate at a low supply voltage of 1 V with a rail-to-rail logic swing and a high voltage gain of approximately −3.0. The exact NOR logic functionality is achieved owing to the superior electrical characteristics of the well-aligned p- and n-NWFETs, which are obtained using conventional Si-based CMOS technology. Moreover, the NOR logic gates exhibit stable characteristics and have good mechanical properties. The proposed bendable NW CMOS NOR logic gates are promising building blocks for future bendable integrated electronics.

In this study, we demonstrate the performance of silicon nanowire (SiNW)n-metal oxide semiconductor (MOS) and p-MOS ratioed inverters that are fabricated on bendable substrates. The electrical characteristics of the fabricateddevices can be controlled by adjusting the load voltage. The logic swings of then- and p-MOS ratioed inverters at a low supply voltage of 1 V are 80% and 96%, respectively. The output voltage level of the p-MOS ratioed inverter is close to rail-to-rail operation. The device also exhibits stable characteristics with goodfatigue properties. Our bendable SiNW ratioed inverters show promise asa candidate building block for future bendable electronics.

Herein, a new combination of high-performance and bias-stress-stable SnO2 thin-film transistors (TFTs) with Y2O3 passivation layers is introduced. The Y2O3 layers on SnO2 semiconductors function suitably as passivation layers to minimize H2O adsorption and to avoid free carrier trapping by creating physical gaps that are larger than the characteristic diffusion length. Yttrium is observed to partially diffuse into SnO2, suppressing the formation of oxygen vacancies in the SnO2 semiconductor because of its low electronegativity and standard electrode potential. The SnO2 TFTs with Y2O3 passivation layers exhibit a mobility of 5.7 ± 0.3 cm2/Vs, subthreshold swing of 1.1 ± 0.2 V/decade, threshold voltage (VTH) of + 6.8 ± 0.4 V, and on/off current ratio of 6.1 (±0.3) × 107. The fabricated sol–gel-processed SnO2 TFTs with Y2O3 passivation layers revealed remarkable negative and positive bias stress stabilities without hysteresis and consistently delivered high performance with enhancement mode operations. Owing to this high performance, the SnO2/Y2O3 combination reported herein has potential as a commercial-product-level TFT for next-generation displays.

In this paper, we present the impact ionization and tunneling operations in a newly designed dopingless device. Our proposed device functions selectively—as either a p-channel impact-ionization MOSFET (p-IMOS) or an n-channel tunneling field-effect transistor (n-TFET)—according to the bias conditions. To realize the dopingless device, the charge-plasma effect is employed to induce n- or p-type regions without any doping process, by choosing an electrode metal with an appropriate work function. The band diagrams, I–V characteristics, subthreshold swings (SS), and carrier-concentration profiles of the device under the p-IMOS and n-TFET operation modes are analyzed in our study, using a commercial device simulator. The device yields an extremely low SS of 0.53 mV/dec under the p-IMOS operation mode. It also exhibits a low off-current of approximately 10−14 A/μm and a high ION/IOFF of approximately 108, under the n-TFET operation mode.

In this study, we demonstrate the static random access memory (SRAM) characteristics generated by weak impact ionization in bendable field-effect transistors (FETs) with n+-p-n+ silicon nanowire (SiNW) channels. Our bendable SiNW FETs show not only superior switching characteristics such as an on/off current ratio of ~105 and steep subthreshold swing (~5 mV/dec) but also reliable SRAM characteristics. The SRAM characteristics originate from the positive feedback loops in the SiNW FETs generated by weak impact ionization. This paper describes in detail the operating mechanism of our device and demonstrates the potential of bendable SiNW FETs for future SRAM applications.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

In this paper, we propose a novel construction of silicon nanowire (SiNW) negative-AND (NAND) logic gates on bendable plastic substrates and describe their electrical characteristics. The NAND logic gates with SiNW channels are capable of operating with a supply voltage as low as 0.8 V, with switching and standby power consumption of approximately 1.1 and 0.068 nW, respectively. Superior electrical characteristics of each SiNW transistor, including steep subthreshold slopes, high I on/off ratio, and symmetrical threshold voltages, are the major factors that enable nanowatt-range power operation of the logic gates. Moreover, the mechanical bendability of the logic gates indicates that they have good and stable fatigue properties.

In this paper, we describe the feedback and tunneling operations of a dual top gate field-effect transistor (FET) with a p

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

In this study, we present an optically tunable feedback field-effect transistor (FBFET) with two independent gates and a p+-i-n+ silicon nanowire. Because of the feedback operation, the FBFET features extremely steep switching characteristics with subthreshold swings alt; 4 mV/dec, and it can be reconfigured as a p- or n-type transistor by controlling the gate-voltage biases. When the FBFET is exposed to a He?Ne laser beam (? = 633 nm), photogenerated carriers accumulate in the potential wells and reduce the potential-barrier height. The optically tunable feedback operation is attributed to this lowering of the potential barrier caused by the light. The triggering voltages can be modulated according to illumination, even when feedback is being provided. This optically tunable transistor with excellent switching characteristics opens up possibilities for application in future optoelectronic devices.

In this paper, we describe the feedback and tunneling operations of a dual top gate field-effect transistor (FET) with a p +-i-n + doped silicon nanowire channel. The transistor functions selectively in either a feedback FET (FBFET) or a tunneling FET mode by modulating the source-to-drain voltage, and it features an outstanding subthreshold swing characteristic of 6.15 mV dec-1 with an on/off current ratio (I on/I off) of approximately 106 in the feedback operating mode and of 41.3 mV dec-1 with I on/I off of ∼107 in the tunneling operating mode. Moreover, our device in the FBFET operation mode has memory characteristics with a retention time of 104 s and a program/erase endurance up to 103 cycles owing to the positive feedback loop in the channel region. This study demonstrates the promising potential of our devices in the development of multifunctional electronics.

In this study, we present the steep switching characteristics of bendable feedback field-effect transistors (FBFETs) consisting of p(+)-i-n(+) Si nanowires (NWs) and dual-top-gate structures. As a result of a positive feedback loop in the intrinsic channel region, our FBFET features the outstanding switching characteristics of an on/off current ratio of approximately 10(6), and point subthreshold swings (SSs) of 18-19 mV/dec in the n-channel operation mode and of 10-23 mV/dec in the p-channel operation mode. Not only can these devices operate in n- or p-channel modes, their switching characteristics can also be modulated by adjusting the gate biases. Moreover, the device maintains its steep SS characteristics, even when the substrate is bent. This study demonstrates the promising potential of bendable NW FBFETs for use as low-power components in integrated circuits or memory devices.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I–V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec−1, an on/off current ratio of approximately 1011, and an on-current of approximately 10−4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

The tribological properties of PTFE composite coatings reinforced by nano-diamonds were investigated. Mechanical particle size reduction and dispersion of nano-diamond aggregates were performed by milling with ceramic beads in an organic solvent. Particle size was controlled by the milling time. Pastes comprising a PTFE solution mixed with nano-diamond having various sizes were coated on the aluminum substrate. Ball-on-plate type wear test was performed to investigate the friction and wear behavior. The results indicated that the addition of nano-diamonds effectively improved tribological performance of the PTFE coating. The reduction in nano-diamond sizes were not always improved the wear resistance of PTFE coating. This unexpected behavior was explained by observation on the worn surfaces and wear debris.