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Although iodine nutrition in Spain has improved in recent years, the problem is not completely resolved. It is necessary that health institutions establish measures to ensure an adequate iodine nutrition of the population, especially among the highest risk groups (children and adolescents, women of childbearing age, pregnant women and nursing mothers). A low salt intake should be advised, but it should be iodized. It is also imperative that food control agencies establish effective control over adequate iodization of salt. Indicators on iodine nutrition should be included in future health surveys. The EUthyroid study and the Krakow Declaration on iodine nutrition provide an opportunity to set up a pan-European plan for the prevention of iodine deficiency that should be considered and used by health authorities. (C) 2019 SEEN y SED. Published by Elsevier Espana, S.L.U. All rights reserved.

Scaling to 45 nm node and below might necessitate the use of new processing steps (e.g. new gate stacks) or new device concepts such as FinFETs. Although intrinsic transistor speed increases with scaling, some analog performance parameters tend to degrade. In this paper we show with experimental results and simulations on analog and RF circuits that for high-speed and RF applications, downscaling to 45 nm channel length of bulk devices still improves RF circuit performance, while for low-frequency, high-gain applications FinFET technology offers better circuit performance than planar bulk CMOS.

Comparison of digital and analog Figures-of-Merit of FinFETs and planar bulk MOSFETs reveals an interesting trade-off in analog/RF design space. It is seen that FinFETs possess key advantages over bulk FETs for applications around 5 GHz where the performance-power trade-off is important. In case of higher frequency applications bulk MOSFETs are shown to hold the advantage on account of their higher transconductance (Gm), provided a degraded voltage gain and a higher leakage current can be tolerated.

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-mu m CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanismsbehind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design

Crosstalk from digital to analog in mixed-signal ICs is recognized as one of the major roadblocks for systems-on-chip (SoC) in future CMOS technologies. This crosstalk mainly happens via the semiconducting silicon substrate, which is usually treated as a ground node by analog and RF designers. The substrate noise coupling problem leads more and more to malfunctioning or extra design iterations. One of the reasons is that the phenomenon of substrate noise coupling is difficult to model and hence difficult to understand. It can be caused by the switching of thousands or millions of gates and depends on layout details. Form the generation side (the digital domain), coping with the large amount of noise generators can be solved by macromodeling. On the other hand, the impact of substrate noise on the analog circuits requires careful modeling at the level of transistors and parasitics of layout, power supply, package, PCB, … Comparison to measurements of macromodeling at the digital side and careful modeling at the analog side, shows that both the generation and the impact of substrate noise can be predicted with an accuracy of a few dB. In addition, this combination of macromodeling at the digital side and careful modeling at the analog side leads to an understanding of the problem, which can be used for digital low-noise design techniques to minimize the generation of noise, and substrate noise immune design of analog/RF circuits.

The past years the market of wireless applications has grown enourmously, driven by the development of high performance, low cost CMOS technologies. This CM”OS evolution allows the integration of an increasing amount of digital and analog functions on a single die, enabling cost and power reduction. In many cases the coupling of digital switching noise via the common die to the analog circuits degrades the overall system performance, sometimes resulting in device failure. An overview of substrate noise coupling issues can be found in [1]. The goal of this Ph.D. research is to fully uncerstand the mechanisms behind the performance degradation of RF circuits due to impact of digital switching noise in order to control and solve the problem.

More and more system-on-chip designs require the integration of analog circuits on large digital chips and will therefore suffer from substrate noise coupling. To investigate the impact of substrate noise on analog circuits, information is needed about digital substrate noise generation. In this paper, a recently proposed simulation methodology to estimate the time-domain waveform of the substrate noise is applied to an 86-Kgate CMOS ASIC on a low-ohmic epi-type substrate. These simulation results have been compared with substrate noise measurements on this ASIC and the difference between the simulated and measured substrate noise rms voltage is less than 10%. The simulated time domain waveform and frequency spectrum of the substrate noise correspond well with the measurements, indicating the validity of this simulation methodology. Both measurements and simulations have been used to analyze the substrate noise generation in more detail. It has been found that direct noise coupling from the on-chip power supply to the substrate dominates the substrate noise generation and that more than 80% of the substrate noise is generated by simultaneous switching of the core cells. By varying the parameters of the simulation model, it has been concluded that a flip-chip packaging technique can reduce the substrate noise rms voltage by two orders of magnitude when compared to traditional wirebonding.

The goal of the research project that is presented in this paper, is the development of a mixed analog/digital silicon compiler. The compiler is targeted to the architectural design of a mixed analog/digital signal acquisition and processing chain for space applications. The user has to describe the functionality and performance requirements of a system to be de signed. The compiler then translates the system description into an architecture of low level modules such as A/D converters, amplifiers and filters, as well as digital control sections. The layouts of the different modules will be generated by dedicated analog or digital module generators. Finally, the compiler assembles the layout of the total system. The necessary verifications at different levels during the design process will be performed by a mixed signal simulator. The general requirements and design flow of the silicon compiler will be discussed, together with the application domain of the compiler.