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The majority of electronic products today are built using no-clean soldering processes. However, the effect of no-clean flux residue on signal integrity is a concern for many high-frequency products, such as fifth-generation (5G) and other communication products. No-clean flux residue can create an alternative path to the signal and degrade the signal integrity performance, especially at high frequency. However, there are limited studies on the effect of no-clean residue on signal integrity. This work sets out to study the effects of no-clean flux residue on signal integrity at high frequency, including the frequency spectrum used for 5G technology. This study includes the analytical modeling of the dielectric loss and impedance mismatch loss at high frequency. In addition, the insertion loss is measured at different frequencies up to 50 GHz. The results show that the loss due to the presence of no-clean flux residue is statistically insignificant within the scope of this study.

This article presents the studies on the launderability of conductive fabrics with four types of metal coatings (Cu, Ag, Ni/Cu, or Ni/Cu/Co), respectively, which are laminated to three common fabrics (spandex, nylon, and denim) using thermoplastic urethane (TPU) film. The electrical resistance as a function of laundry cycles is used to characterize the performance of these conductive materials. The laundry procedure follows the AATCC M6 test standard by using the AATCC compliant washer and dryer with control factors such as detergent, temperature, agitation speed, and spin speed. After the intended wash and dry cycles, the electrical resistance of the conductive fabrics is measured using a four-point probe method. The resistance stability over the laundry cycles is compared between these conductive fabrics with four metal coatings, respectively. In general, all the conductive fabrics show an increase in electrical resistance with laundry cycles, and the extent of the increase depends on the metal coating and the base fabrics to which the conductive fabrics are laminated. Further, the soaking test reveals that the AATCC certified detergent does not have a measurable effect on the performance of the conductive fabrics. To obtain an insight on the degradation of the conductive fabrics during laundry, further inspection and analysis are performed, including 3-D optical microscopy, scanning electronic microscopy (SEM), cross sectioning, and X-ray fluorescence (XRF). A significant peeling and fracture of metal coating layers, due to mechanical tumble or agitation stresses during laundry, are observed for the conductive fabrics with Cu, Ni/Cu, and Ni/Cu/Co coatings, leading to electrical resistance increase or even electrical open, whereas the conductive fabrics with Ag coating show a metal scratch instead of peeling and fracture, possibly due to silver’s superior flexibility, ductility, and adhesion with the base fiber. Besides metal coatings, the mechanical properties of the base fabrics appear to significantly affect the laundry performance of the conductive fabrics, in which the more rigid base fabric causes higher mechanical stresses on the metal coating, leading to more damages and accordingly higher increases in resistances.

To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also facilitates integration of multiple dies vertically and horizontally in a single package without using substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in eWLB fan-out WLP with multilayer RDL's. Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Warpage, die cracking and other failures were characterized through metrology measurements and electrical tests. Board assembly processes (including SMT, underfill, etc.) were also studied. The influence of materials and structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.

In this paper, we present a complete 700---2,600 MHz RF SiP module for micro base station. This RF SiP design integrates transmitter, receiver, feedback module, ADC/DAC and CLK module. The module consists of two multi-layer organic substrates that are vertically stacked using BGA interconnections. With the integration of 33 chips and about 600 passive components, this RF SiP module retains small form factor and measures 5.25 cm × 5.25 cm × 0.7 cm. The RF input signal transmission path insertion loss is less than 0.34 dB and the return loss is less than ?14 dB at 2.6 GHz. Full load thermal simulation result indicates that each chip junction temperature is below 100 °C. We summarize the RF SiP module design, assembly and simulated thermal characteristics. The proposed RF SiP can generally be characterized by small size, low cost and short development cycle.

The bi-directional data rate is investigated of an eight-channel × 10-Gbps optical transceiver with a size of 15 mm × 15 mm × 6 mm and ball grid array package form that was designed and fabricated. A passive optical coupling method is designed based on a coupling lens array, which is transformed to substrate through a carrier. This electrical performance is characterized through a 3D full wave simulation and shows great advantages compared with traditional pluggable optical transceivers. Experimental eye diagram measurement in loop-back mode via a 2-m-long multi-mode fiber array shows an eye width of 51.984 ps at a bit-error rate order of 10−12, which proves the transceiver's ability for 10.3125-Gbps data transmission.

PurposeAs a literature review article, the purpose of this paper is to highlight the intricate interaction and correlation between the interconnection microstructure and the failure mechanism. It is therefore critical to summarize all the challenges in understanding solder solidification of interconnections.Design/methodology/approachLiterature review.FindingsSolidification of solder interconnections is therefore critical because it is the process during which the solder interconnection is formed. The as‐solidified microstructure serves as the starting point for all failure modes. Because of the miniaturization of electronics, the interconnection size decreases continuously, already to such a range that solder solidification takes place remarkably differently from the bulk ingot, on which solidification studies have been focused for decades. There are many challenges in understanding the solidification of tiny solder interconnections, including the complex metallurgical system, dynamic solder composition, supercooling and actual solidification temperature, localized temperature field, diverse interfacial IMC formation, and so on, warranting further research investment on solder solidification.Originality/valueThis paper provides a critical overview of the concerns in solidification study for lead‐free solder interconnection. It is probably an article initiating more attention towards solidification topics.

Pad cratering of printed circuit board (PCB) is becoming a prevailing issue encountered in the PCB assemblies which is accelerated when switching to leadfree process. These units with pad cratering may not fail during functional test as and raise potential failure in the field. This paper uses both experimental and finite element analysis (FEA) approaches to understand the pad strength and pad stresses. An extensive mechanical test by pin pull tests are performed on PCB materials. Cohesive elements are employed to simulate the bonding at the interfaces of pad, laminate and fibers. The results from FEA show that the laminate cracking can be successfully simulated. The design variables such as traces and solder fillet impact are also critical for pad cratering.

PurposeThe purpose of this paper is to consider PTH solder joint reliability, particularly on the PTH solder joints with partial hole‐fill and without pin protrusion. Also, the impact of voiding on the solder joint reliability is discussed.Design/methodology/approachThermal cycling tests for samples of different hole‐fill percentages and voiding were conducted, and cross‐sections of the PTH solder joints were performed to evaluate the solder microstructure, intermetallic formation, via hole‐fill, and the condition of the PTH metallization and PCB dielectric prior to thermal cycling and at different times during thermal cycling.FindingsDifferent failure mechanisms were observed for solder joints with and without pin protrusion. PTH components with pin protrusion had better through hole‐fill and less voids than PTH components without pin protrusion.Originality/valueThe paper discusses in detail the effect of hole‐fill percentage and voiding on PTH solder joint reliability.

The compatibility of lead-free area array packages with tin-lead soldering processes is a critical issue, as several product categories may take advantage of the exemptions under the European Union (EU) RoHS legislation and continue to be built with tin-lead solder for some time to come, whereas the components have become predominantly lead-free. The issue of "backward compatibility" arises because for BGA packages, the contribution of solder balls to the resultant solder joint material is very high (typically of 70% to 80%), and the assembly of lead-free BGA packages with tin-lead paste becomes a major concern from the perspective of solder joint metallurgical uniformity and reliability. This paper presents a comprehensive study on the effects of critical process conditions on solder joint metallurgy and reliability of mixed alloy solder joints. The solder joint metallurgy of mixed alloys was characterized and the lead distribution through the solder joint was analyzed, for different package types and under various process conditions. The results showed that the solder paste amount (ultimately the tin percentage, Sn% in the alloy) and the reflow temperature play critical roles in the mixed alloy assembly, both in terms of compositional homogeneity and voiding. The reliability of mixed alloy solder joints was then studied at various process conditions, under different thermal and mechanical stress environments. The study revealed that the sensitivity of the reliability of the mixed alloy solder joints to the process condition depends on the type of environmental loading.

This paper presents a study of the optimization of the gold plating thickness for the use of both wire bonding and soldered interconnects on a flexible printed circuit board sample module. Wire bondability is typically better, when the gold plating thickness is greater than 30 μin.; however, the risk of problems with solder joint embrittlement becomes a concern with thick gold plating. In order to better understand the effect of the gold plating thickness on wire bondability and solder joint embrittlement, an evaluation was performed on samples with three ranges of gold plating thicknesses (10–20 μin., 20–30 μin., and 30–45 μin.), on flexible printed circuit board (PCB), substrates. Mechanical shear testing and metallurgical analyses were conducted on chip component solder joints in this three thickness gold study. Thermal shock and drop testing were conducted to evaluate the reliability of the sample modules. Drop testing is especially critical for determining the reliability of the sample modules, which are used in portable consumer electronics products. Reliability testing and metallurgical analyses have been performed to characterize the effect of gold embrittlement on the mechanical integrity of the solder joints with a gold content ranging from 1 to 4 wt.%.

In this study, failure analysis of the 1657CCGA package with 95.5wt%Sn3.9wt%Ag0.6wt%Cu and 63wt%Sn37wt%Pb solder pastes on lead-free PCBs with the Entek OSP (organic solderability preservative) surface finish is investigated. Emphasis is placed on determining the failure locations and failure modes of the solder joints of the 1657CCGA assemblies after they have been through 7,000 cycles of temperature cycling.

In this paper, the coupling effect in Sn–3.5Ag–3.0Bi and Sn–8.0Zn–3.0Bi solder joint with sandwich structure by long time reflow soldering was studied. It was found that the interfacial compound at the Cu substrate was binary Cu–Sn compound in Sn–Ag–Bi solder joint and Cu5Zn8 phase in Sn–Zn–Bi solder joint. The thickness of the Cu–Zn compound layer formed at the Cu substrate was greater than or equal to that of Cu–Sn compound layer, although the reflow soldering temperature of Sn–Zn–Bi (240 °C) was lower than that of Sn–Ag–Bi (250 °C). The stable Cu–Zn compound was the absolute preferential phase in the interfacial layer between Sn–Zn–Bi and the Cu substrate. The ternary (Cu, Ni)6Sn5 compound was formed at the Sn–Ag–Bi/Ni(P)–Cu metallization interface, and a complex alloy Sn–Ni–Cu–Zn was formed at the Sn–Zn–Bi/Ni(P)–Cu metallization interface. It was noted that Cu atoms could diffuse from the Cu substrate through the solder matrix to the Ni(P)–Cu metallization within 1 min reflow soldering time for both solder systems, indicating that just 30 s was long enough for Cu to go through 250 μm diffusion length in the Sn–Ag–Bi solder joint at 250 °C. The coupling effect between Ni(P)/Cu metallization and Cu substrate was confirmed as the type of IMCs at Ni(P) layer had been changed from Ni–Sn system to Cu–Sn system apparently by the diffusion effect of Cu atoms. The (Cu, Ni)6Sn5 layer at the Ni(P)/Cu metallization grew significantly and its thickness was even greater than that of the Cu–Sn compound on the opposite side, however the growth of the complex alloy including Sn, Ni, Cu and Zn on the Ni(P)/Cu metallization was suppressed.

PurposeTo investigate effects of the thermal history on intermetallic thickness and morphology and on the resulting shear strength of the ball attachment for a variety of BGA components.Design/methodology/approachIn this study, a variety of BGA components with balls made of Pb‐free Sn‐Ag‐Cu (SAC) 305, Sn‐Pb eutectic and high‐temperature 90Pb‐10Sn alloys, were subjected to different thermal histories, including up to ten reflow cycles, and aged at 125°C from 24 to 336 h. The intermetallic thickness and morphology after these thermal events were then examined under optical and scanning electronic microscopes. Ball shearing tests were conducted to investigate effects of the thermal history and intermetallic thickness and morphology on shearing strength of these solder balls.FindingsThe results show that effects directly from intermetallic layers may or may not be detectable; and the shear strength of solder balls is largely dependent on the solder alloy and its microstructure. Shear strength increases are observed after multiple reflow cycles and ageing at elevated temperature for the two Pb‐bearing alloys, while the SAC305 lead‐free alloy shows slight reductions in both strength and ductility after thermal exposure.Practical implicationsPresented results can be used for estimation of reliability for electronic assemblies subjected to multiple rework and repair operations, which expose sensitive components, such as BGAs, to elevated temperatures.Originality/valueIt is believed that a sound understanding of the effects of intermetallic morphology and thickness on reliability of BGA solder balls can lead to more intelligent choice of soldering processes, as well as to rework/repair process optimisation and to establishing their operational limits.

Since high speed digital signal interconnection usually consists of differential transmission lines and pairs of via, signals passing through pairs of via need carefully handling for via can be either capacitive or inductive. The modeling of high speed via is critical to match the impedance of a pair of via and differential transmission line. Parasitic parameters of a pair of via such as capacitances and inductances can be extracted by Q3d, a high performance EM parameter extraction software. Several variables are analyzed: the diameter of via, pad, anti-pad, space between the pair of via and position of ground via around the differential signal via. From the simulation results, parasitic parameters have a significant change with these variables changed. At the same time, TDR (Time domain reflection) and S parameter are also simulated by HFSS to verify the parasitic parameter's effects. Parameter extraction and modeling with a pair of via is a helpful way for via optimization, which is commonly used in high speed digital signal interconnection, high frequency transceiver and many application areas.

Electromagnetic interference (EMI) has become a remarkable and negligible problem in SiP module. As package tend to higher density and smaller size, the electromagnetic environment become complex and severe. The shortening distance between different devices in SiP enhances the EMI between different devices. Shielding methods in SiP, especially in 3D package, are worth researching. In this paper, a conformal shielding structure with conductive adhesive is researched. The conductive adhesive is coated on the flip-chip dies and connected to ground plane on the top of the substrate. In order to research the shielding effectiveness of this shielding structure, we construct two models in the 3D full wave electromagnetic simulator HFSS, one with shielding structure, and the other without shielding structure. After simulation, we obtain the distribution and the value of the radiation field at 1mm above the flip-chip die. After analysis and calculation, we get the shielding effectiveness of 16–36dB at 1GHz and 20–48dB at 3GHz.

The Sn-3.5Ag and Sn-4.0Ag-0.5Cu solders on electroless Ni-immersion Au metallization exhibited different interfacial morphology after high temperature storage (HTS) testing at 150/spl deg/C. Ni/sub 3/Sn/sub 4/ intermetallic compounds (IMCs) were found in the Sn-Ag system, while in the Sn-Ag-Cu system, spalling grains of (Cu,Ni)/sub 6/Sn/sub 5/ IMC were observed after long aging, along with a thick (Ni,Cu)/sub 3/Sn/sub 4/ IMC layer which adheres to the P rich electroless Ni coating. Kirkendall voids were found between the Sn-Ag and electroless Ni interface after 168 and 500 hour thermal aging, while a clear gap existed at the interface after 1000 hour aging, as a result of the growth of the micro-voids. In the Sn-Ag-Cu system, Kirkendall voids were found inside grains of the Sn-Ni-Cu ternary interfacial compound after 500 and 1000 hour aging.

The interfacial reactions between Sn-0.4Co-0.7Cu eutectic alloy and immersion Au/electroless Ni(P)/Cu substrate were investigated after reflow soldering at 260 °C for 2 min. Common Sn-4.0Ag-0.5Cu and eutectic Sn-0.7Cu solders were used as reference. Two types of intermetallic compounds (IMC) were found in the solder matrix of the Sn-0.4Co-0.7Cu alloy, namely coarser CoSn 2 and finer Cu 6 Sn 5 particles, while only one ternary (Cu, Ni) 6 Sn 5 interfacial compound was detected between the solder alloy and the electroless nickel and immersion gold (ENIG) coated substrate. The same trend was also observed for the Sn-Ag-Cu and Sn-Cu solder joints. Compared with the CoSn 2 particles found in the Sn-Co-Cu solder and the Ag 3 Sn particles found in the Sn-Ag-Cu solder, the Cu 6 Sn 5 particles found in both solder systems exhibited finer structure and more uniform distribution. It was noted that the thickness of the interfacial IMCs for the Sn-Co-Cu, Sn-Ag-Cu and Sn-Cu alloys was 3.5 μm, 4.3 μm and 4.1 μm, respectively, as a result of longer reflow time above the alloy's melting temperature since the Sn-Ag-Cu solder alloy has the lowest melting point. © 2006 Elsevier B.V. All rights reserved.

PurposeThis paper aims to describe and document the application of commonly utilized solder joint failure analysis techniques to lead‐free solder joints.Design/methodology/approachTraditional failure analysis techniques, including visual inspection, X‐ray radiography, mechanical strength testing, dye and pry, metallography, microscopy and photomicrography, are reviewed. These techniques are demonstrated as applied to lead‐free and tin lead solder joints. Common failure modes observed in lead‐free and tin lead solder joints are described and compared.FindingsIt is shown that the traditional failure analysis techniques previously utilized for tin lead solder joints are widely applicable to the analysis of lead‐free solder joints. The changes required to effectively apply these techniques to the analysis of lead‐free solder joints are described.Originality/valueThis paper will be instrumental to the process, quality, reliability and failure analysis engineering disciplines in furthering understanding of the application of failure analysis techniques of both tin lead and lead‐free solder joints.

PurposeTo determine the Coffin‐Manson (CM) equation constants for fatigue life estimation of Sn‐8Zn‐3Bi solder joints, since Sn‐8Zn‐3Bi solder has a melting temperature of around 199°C which is close to that of the conventional Sn‐Pb solder which has previously been used in the electronics assembly industry.Design/methodology/approachThree dimensional finite element (FE) simulation analysis was used for comparison with the experimentally measured data and to determine the CM constants. Low cycle fatigue tests and FE simulations were carried out for these lead‐free solder joints, and eutectic Sn‐37Pb solder was used as a reference.FindingsThe CM equation for Sn‐8Zn‐3Bi solder joints was fitted to the lifetimes measured and the shear strains simulated. The constants were determined to be 0.0294 for C, the proportional constant, and for the fatigue exponent, β, −2.833.Originality/valueThe CM equation can now be used to predict the reliability of Sn‐8Zn‐3Bi solder joints in electronics assembly and the knowledge base for the properties of the Sn‐Zn solder system has been increased.

For double-sided assemblies, the solder joints on the topside of the board are inverted and reflowed again. During the second reflow, the components are held in place by the surface tension, which may prevent the components from falling off under the gravitational force. A method is needed to determine a component’s candidacy for bottom-side attachment based on the component weight and total pad area. In this paper, a theoretical model was introduced to determine the critical value for component fall-off during the second reflow. Design of Experiments (DOE) and ANOVA analysis for lead-free solder boards were performed to examine the main process factors which have different effects on the component fall-off for different components, and comparison was made between lead-free and SnPb solders. Optical inspection and cross-sectioning were carried out for further investigation. The test results indicated no significant difference of Cg=Pa value between SnPb and lead-free solders. [doi:10.2320/matertrans.47.1577]

The wetting of a molten solder on metallic surfaces is a rather complex phenomenon. In addition to physical spreading due to surface tension reduction, there are interfacial metallurgical and flux chemical reactions with the metallic substrate surface. Substrate dissolution and intermetallic formation take place rapidly during soldering. Since lead-free soldering requires substantially higher soldering temperatures (around 250 � C), the rates of intermetallic growth and substrate dissolution for lead-free solders are expected to be significantly greater than those for the current Sn–Pb eutectic solder. This study systematically investigates the metallurgy of the solid–liquid interface reactions and intermetallic growth kinetics for three lead-free solders: Sn–Ag eutectic (96.5%Sn–3.5%Ag), Sn–Cu eutectic (99.3%Sn–0.7%Cu) and Sn–Ag– Cu eutectic (Sn–3.8Ag–0.7Cu, SAC 387) with three metallic substrates: Cu, Ni, and Alloy 42 (42%Ni–52%Fe) over temperatures ranging from 225 to 280 � C for reaction time from 10 s to 16 h. Wetting behavior of these three alloys on PCBs with OSP, immersion Sn, and Ni/Au finishes, was also examined from 220 � C up to 260 � C. A thorough understanding of lead-free solder/substrate interfacial reactions should give guidance to the optimum lead-free soldering processes and to the optimum lead-free coating thicknesses for component and PCB terminal finishes, as well as for under-chip metallurgical coatings for flip-chip and BGA applications.

Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700–2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.

PurposeProvide information on the effects of flux residues from surface mount assembly on radio frequency (RF) performance.Design/methodology/approachA series of test vehicles designed to evaluate the RF performance on various test patterns and some simple circuits. Empirical testing is used in determining the data.FindingsProvides a methodology for checking the performance of flux residues as well as information on the performance of a few different flux residue types.Research limitations/implicationsThis is not an all encompassing project and the results may not extrapolate out to higher frequency ranges.Practical implicationsA good source of reference that can be used to understand the impacts of the assembly process on RF performance.Originality/valueThis paper shows the effect of assembly materials (flux residues) on a real circuit and not just test patterns. It can give a basic understanding to process engineers of the potential impact of the assembly process on a RF circuit.

Reliability of lead-free solder joints has been a hot topic widely debated in the electronic industry. Most published data indicate that a change to lead-free soldering has the potential benefit of more reliable solder joints than the current Sn-Pb eutectic solder joints. However, in reality many mechanical, metallurgical, thermal, and environmental factors affect the service reliability of solder joints. This paper tries to shed some light on the effects of mechanical loading and thermal conditions on solder joint reliability. These conditions are determined not only by external environments but also by the solder alloy itself and the joint geometry. Analyses with first principles are carried out on solder joints of both areal array and peripheral packages. Effects on fatigue life of solder joint geometry, thermal and mechanical characteristics of components and substrate materials, and application conditions are discussed. The analysis helps explain why lead-free solder joints may not be more reliable in certain application conditions than the current Sn-Pb eutectic solder joints.

The surface mount technology (SMT) assembly process for 0.4 mm pitch chip scale package (CSP) components was studied in this work. For the screen printing process, the printing performance of different solder pastes, aperture shapes and sizes was investigated. Square apertures and a fine particle size in the solder paste provided a better paste release. Besides optimising the printing process capability and minimizing the printing defects such as bridging and missing paste, the total volume of solder consisting of the paste and the solder ball has to be considered in order to maximize the final process yield. For the pick & place process, the accuracy required for the placement equipment was determined by studying the self‐alignment of the lead‐free CSPs (with Sn/4.0Ag/0.5Cu balls) during the reflow process using lead‐free Sn/3.9Ag/0.6Cu paste. The components were intentionally misplaced up to ∼50percent off‐pad. After reflow, x‐ray inspection showed that the components had aligned to the pad. By consider...

The wetting of I-Ag (immersion silver) and I-Sn (immersion tin) printed-circuit-board (PCB) finishes by Sn/Ag/Cu and eutectic Sn/Pb solders was studied in this work with Ni/Au (electroless nickel/immersion gold) and organic solderability preservative (OSP) finishes as baselines. Wetting tests were performed on fresh boards and boards subjected to different preconditioning treatments that simulated the effects of aging, storage, and multiple reflow cycles. When the boards are fresh, the wetting of the I-Sn and Ni/Au finishes is better than that on the I-Ag and OSP finishes. However, after the preconditioning treatments, the wetting of the I-Sn finish degrades the fastest, whereas the wetting of the I-Ag and OSP finishes degrade less through the different preconditioning treatments. The wetting of the Ni/Au finish remains excellent through all the preconditioning treatments. The chemical and microstructural changes in the finishes during aging treatments were evaluated using electron spectroscopy chemical analysis (ESCA), x-ray diffractometry (XRD), and cross-sectioning followed by scanning electron microscopy (SEM). The results indicate that a single lead-free reflow cycle consumes the I-Sn layer faster than a Sn/Pb reflow cycle because of the formation of the Sn/Cu intermetallic compound (IMC). Consequently, I-Sn finished boards having an original Sn thickness of ∼1 µm will not withstand multiple lead-free reflow cycles without significant degradation in wetting but up to two Sn/Pb reflow cycles are still feasible. The minimum thickness of I-Sn required for adequate wetting was evaluated by comparing the wetting after different aging treatments. The exposure of I-Sn samples to 85°C/85% relative humidity (RH) conditions increases the thickness of the Sn-oxide layer, which, above a certain thickness, can degrade wetting. Oxidized copper areas formed on top of the I-Ag surface after exposure to 85°C/85% RH treatment, and this was considered a major factor influencing wetting. The formation of sulfides on I-Ag was detected, but their overall quantity remained too small to have a detectable impact on the wetting.

Failure analyses of the lead‐free and SnPb solder joints of high‐density packages such as the plastic ball grid array and the ceramic column grid array soldered on SnCu hot‐air solder levelling electroless nickel‐immersion gold or NiAu, and organic solderability preservative Entek printed circuit boards are presented. Emphasis is placed on determining the failure locations, failure modes, and intermetallic compound composition for these high‐density packages' solder joints after they have been through 7,500 cycles of temperature cycling. The present results will be compared with those obtained from temperature cycling and finite element analysis.

Temperature cycling tests, and statistical analysis of the results, for various high‐density packages on printed‐circuit boards with Sn‐Cu hot‐air solder levelling, electroless nickel‐immersion gold, and organic solder preservative finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and reliability of the lead‐free solder joints of these high‐density package assemblies while they are subjected to temperature cycling conditions. A data acquisition system, the relevant failure criterion, and the data extraction method will be presented and examined. The life test data are best fitted to the Weibull distribution. Also, the sample mean, population mean, sample characteristic life, true characteristic life, sample Weibull slope, and true Weibull slope for some of the high‐density packages are provided and discussed. Furthermore, the relationship between the reliability and the confidence limits for a life distribution is established. Finally, the confidence levels for comparing the quality (mean life) of lead‐free solder joints of high‐density packages are determined.

The mechanical properties of Sn/Ag/Cu solder joints in combination with different component lead coating materials (Ni/Pd/Au, Sn/15 per cent Pb, Sn/2 per cent Bi, and Sn) are studied in this work using a lead pull test and free fall drop test. The results of this study show that the Sn/2 per cent Bi coated components provide the best performance under the drop impact loading followed by the Sn/15 per cent Pb, Sn and Ni/Pd/Au coated components. Failure modes and the structure of the coating surfaces were examined from cross‐sectioned samples using a scanning electron microscope. Furthermore, the wetting of the leads by the solder and thickness of the IMC layers were studied.

The High Density Packaging Users Group conducted a substantial study of the solder joint reliability of high‐density packages using lead‐free solder. The design, material, and assembly process aspects of the project are addressed in this paper. The components studied include many surface mount technology package types, various lead, and printed circuit board finishes and paste‐in‐hole assembly.

The lead‐free solder joint reliability of several printed circuit board mounted high‐density packages, when subjected to temperature cycling was investigated by finite element modelling. The packages were a 256‐pin plastic ball grid array (PBGA), a 388‐pin PBGA, and a 1657‐pin ceramic column grid array. Emphasis was placed on the determination of the creep responses (e.g. stress, strain, and strain energy density) of the lead‐free solder joints of these packages.

0201 assembly plays a very important role in the continuing miniaturization of electronics products. After a systematic study using Sn‐Pb solder paste on pad design, machine evaluation, component qualification, and process optimisation, this study focused on the PCB assembly process for 0201 packages using Sn‐Ag‐Cu solder paste. The post‐reflow solder defects for a range of different spacings were examined for the different solder pastes.

Solder balling in Sn/Ag/Cu solder pastes was studied in this work. Three different solder pastes, several different reflow profiles and conditions, and two stencil thicknesses were used in the investigation. During the first phase, called the verification phase, the solder pastes were checked to ensure they met the minimum requirements. In the process-screening phase, the reflow profile was varied. Results show that besides flux chemistry, reflow atmosphere plays the major role in solder balling. The average number of solder balls with the best paste was one fifth of that with the worst paste. Furthermore, with all the pastes, the number of solder balls dropped close to zero when nitrogen atmosphere was used. Another finding during the reflow process screening was the influence of the stencil thickness on the solder-balling result. With a thinner stencil, two of the pastes exhibited significant solder balling. This is assumed to be caused by the different ability of fluxes to withstand oxidation during the preheating in the reflow process. In the last phase, the effect of the solder-paste particle size on solder balling was studied more closely. The flux chemistry was kept unchanged, and the solder particle size was varied between type 3 and type 4. The results show that, with type 4 paste, significantly more solder balls are formed compared to type 3 paste. It was also confirmed that, regarding the reflow profile, the ramp-up rate from 150°C to 217°C and the reflow atmosphere were the most significant factors that determine the solder-ball formation for both types of paste.

Lead-free wave soldering was studied in this work using a 95.5Sn/3.8Ag/0.7Cu alloy. A process DOE was developed, with three variables (solder bath temperature, conveyor speed, and soldering atmosphere), using a dual wave system. Four no-clean flux systems, including alcohol- and water-based types, were included in the evaluation. A specially designed "Lead-Free Solder Test Vehicle", which has various types of components, was used in the experiments. Both organic solderability preservative (OSP) and electroless nickel/immersion gold (Ni/Au, or ENIG) surface finishes were studied. Soldering performance (bridging, wetting and hole filling) was used as the responses for the DOE. In addition, dross formation was measured at different solder bath temperatures and atmospheres. Dross formation with Sn/Ag/Cu bath was compared to that with eutectic Sn/Pb bath. Regarding the connector-type component, a pad design giving the best soldering performance was evaluated based on the DOE results. Finally, a confirmation run with the optimum flux and process parameters was carried out using the Sn/Ag/Cu solder, and a comparative run was made with the Sn/Pb solder alloy and a no-clean flux used in production. The soldering results between the two runs indicate that with optimum flux and process parameters, it is possible to achieve acceptable process performance with the Sn/Ag/Cu alloy.

The wetting performance and intermetallic formation of a Sn/Ag/Cu alloy on printed circuit board (PCB) surfaces and on component terminations were studied in this work. Two different PCB surface finishes, immersion gold over electroless nickel (Ni/Au) and an organic solderability preservative (OSP), were studied. Chip components with Sn/Pb coating and a gull‐wing type component with 100% Sn coating were used in these experiments. Different reflow profiles were tested, and the dependence of the wetting performance, intermetallic layer thickness and the microstructure of the solder joints on the reflow profile were investigated.It was found that reflow process conditions did not significantly influence the spreading or intermetallic formation on either of the surfaces. Neither the wetting onto the component nor the general microstructure of the solder joints varied significantly with the reflow profile. When a Sn/Pb ‐coated component was used, the content and size of Pb‐rich phases in the solder joint increased with a longer time above liquidus or a higher reflow peak temperature.

This paper discusses the application of conductive wafer bonding, especially wafer level hybrid Cu-Cu bonding, for realizing high density inter-chip interconnection. 3D integration process using conductive wafer bonding and the test vehicle for bonding process evaluation are described. Different pre-bonding surface treatment methods and bonding procedures are studied and compared for yield and throughput optimization.

A band-pass-filter (BPF) based on silicon substrate was designed and simulated. Different software was applied to design and simulate the character of the filter. A three-order filter was designed dedicating to range 2.4 GHz-2.5 GHz use. The ideal topology circuit was designed with passive inductors and capacitors. Moreover, the integrated passive devices (IPDs) were modeled and simulated with thin film process. To enhance the performance of the IPD, some typical factors were considered to optimize the physical model. The IC design tool and electromagnetic simulation software were used and compared to analysis the character of the filter, which demonstrated that the BPF can be applied to RF front-end system.

With the increasing need of smaller size and lower cost of wireless communication system, the integrated passive devices (IPDs) have offered a proper solution. However, small Q factor (quality factor) of integrated passive inductors seriously limits the performance of the IPDs. In this paper, a simplified circuit model of the inductor structure has been presented to extract the parasitic parameters and offer better physical understanding. Moreover, the structure of planer spiral inductors has been optimized by using smaller bars and changing the width and space of the inductor, so as to enlarge the Q factor.

TSV (through-silicon-via) has been regarded as a key technology for 2.5D and 3D electronic packaging. However, the manufacturing of the through silicon interposer (TSI) is very challenging and costly. The minimization of the warpage of the TSV interposer wafer is crucial for successful subsequent processing, for example, thin wafer handling, backside via revealing and copper pillar bumping. In this paper, warpage was tested before and after most of the backside process steps. Wafer level warpage modeling methodology has been developed by finite element analysis (FEA) using equivalent material model. The warpage was simulated and analyzed by considering different process factors.

In this paper, a new high performance three dimensional radio frequency package on package (3D RF PoP) based on ceramic substrate is designed for micro base station which is able to cover the multicasting of critical messages to as many mobile users as possible even under communications network failure events, such as the failure of macro base stations. The RF PoP integrates receiver (RX) module, transmitter (TX) and digital predistortion (DPD) module, and analog-to-digital/digital-to-analog (AD/DA) and clock (CLK) module vertically, has better signal integrity and faster data-rate transfer due to shorter signal paths among the three modules. Additionally, the ceramic substrate has higher thermo-mechanical reliability and better heat dissipation performance compared with organic substrate. The paper firstly studies the thermal performance of the RF PoP without external heat sinks using commercial software ANSYS Icepak. At the ambient temperature of 25 °C, the highest junction temperature of the RF PoP is 239.8 °C, which is above the acceptable baseline for a silicon chip. Secondly, in order to improve the heat dissipation capability of the RF PoP, a large copper bottom heat dissipation plate is employed. The impact of bottom heat dissipation plate on the thermal performance of the RF PoP is investigated. It is found that a bottom heat dissipation plate of 200×200×2 mm 3 is reasonable, and the highest junction temperature is about 47.0 °C. Thirdly, we study the thermal performance of the entire and internal package structure of the RF PoP mounted on the bottom heat dissipation plate. The temperature distributions of the top and middle substrates are almost uniform. Heat generated from active devices on the top and middle packages is mainly transferred to the edges, conducted to the bottom heat dissipation plate through the edges and bottom substrate and heat slug, heat generated from active devices on the bottom package is conducted to the bottom heat dissipation plate through the bottom substrate and heat slug, and then dissipated into the ambient by natural convection, so that the temperature at the edge of the bottom substrate is higher than the other parts. Lastly, the effect of different ambient temperatures on the thermal performance of the RF PoP is investigated. When the bottom heat dissipation plate size is 200×200×2 mm 3 and the ambient temperature reaches 100 °C, the highest junction temperature is about 121 °C. In order to further improve heat dissipation capability of the RF PoP, a copper top heat spreader is employed. The simulation result shows that the junction temperature drops to about 115.6 °C.

Electromagnetic isolation is a critical issue to the performance of radio frequency system in package (RF SIP). This paper proposes a novel structure to measure the electromagnetic (EM) isolation property and to test the shield efficiency of a metal cap. The 3-dimensional structure contains 5 antenna chips assembled is based on rigid and flexible substrates. EM interference and EM isolation relevance with different distances is revealed with ideal antenna simulation results in order to eliminate the parasitic effects. EM isolation properties in different horizontal distances are measured between different chips. Moreover, EM isolation properties in different vertical distances are measured using a structure like a pulley block. This paper also demonstrates EM isolation properties of a shield structure with a metal cap. The test results show the shield efficiency of a metal cap reaches more than 50dB. These results are constituent with the simulation results simulated by HFSS, a 3-dimensional electromagnetic field simulation software.

Glass is an ideal material for 2.5D packaging application with excellent electrical, optical and mechanical properties. In this paper, several forms of coplanar waveguide (CPW) on glass substrate were modeled and simulated using 3D full-wave finite element method (FEM). The target of this research was to provide guidance for the design and analysis of CPW on glass substrate. Analyses of CPWs on different redistribution layers (RDLs) with various line lengths are presented. And the comparison of the performances of CPWs on silicon substrate and glass substrate are also described in this paper. The simulation results illustrate the electrical performances of CPWs on glass substrate are much better than on silicon substrate, especially in high frequency range.

Passive devices are widely used in all kinds of systems. Generally, most of the passive components in an electronic system are assembled as discrete components or passive arrays. Bu t a discrete passive component occupies a lot of space for the realization of its function. To overcome this shortcoming, one promising way is the integration of passive components into system in package. In this paper, we designed two kinds of thin film spiral inductors on both silicon and glass substrates. One is monolayer structure and, another has double layers. The inductors we re modeled and simulated using Finite Element Method (FEM). And, the electrical analysis was performed by ANSYS HFSS an dQ3D.

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.

In this study, thermal cycling reliability tests and analysis for micro solder bump in 2.5D packaging were conducted. Finite element analysis modeling of micro bump with different intermetallic compound (IMC) thickness was developed to model the effect of IMC layer on fatigue behavior of micro bumps. It was found that stress in solder increased notably when the IMC layer is taken into consideration, and increased slightly as further increase in the IMC thickness. The thermal mechanical stress in IMC layer was also studied to assess the reliability of IMC integration. It was found that the stress decreased sharply with the increase of IMC thickness; when all the solder transformed into IMC, the thermal mechanical stress decreased to only 20% of the stress in 1μm IMC. Failure mode after thermal cycling tests was analyzed by cross section morphology. Cohesive cracks in the solder took place at the interface of tin solder and IMC layer, and heavier damage was found in bumps with thicker IMC thickness, which agreed well with the FEA results.

This paper describes a modified finite element method (MFEM) for determining the static equilibrium shape of the capillary surface of a liquid with a prescribed volume constrained by rigid boundaries with arbitrary shapes. It is assumed that the liquid is in static equilibrium under the influence of surface tension, adhesion, and gravity forces. This problem can be solved by employing the conventional FEM; however, a major difficulty arises due to the presence of the volume (integral) constraint and usually requires the use of the Lagrange multiplier method, the sequential unconstrained minimization technique, or the augmented Lagrange multiplier method. With the MFEM, the space variables defining the equilibrium surfaces (or curves) are expanded in terms of parametric interpolation functions, which are designed such that the boundary conditions and the integral constraint equation are automatically satisfied during each iteration of a direct numerical search process. Hence, there is no need to include Lagrange multipliers and/or penalty factors and the problem can be treated more simply as one involving unconstrained optimization. This investigation indicates that the MFEM is more efficient and reliable than the other methods. Results are presented for several case study problems involving liquid solder drops. Copyright © 2000 John Wiley & Sons, Ltd.

The thermomechanical behaviors of a new lead free solder and eutectic 63Sn37Pb are investigated in this paper. A series of tests including tensile, creep, and fatigue, are carried out on a computer controlled 6-axis mini-fatigue tester. The thin strip specimen is used in this research, which is specially designed and verified to be suitable for the testing of solder alloys and comparable to the data from the literature. Based on the experimental study, the new lead free solder alloy shows very attractive characteristics and may have potential applications in electronics packaging products.

Understanding crack growth in solder joints is important for predicting the fatigue life of solder interconnects. In this paper, crack propagation in solder joints made of two solder alloys, 62Sn/36Pb/2Ag (by weight), a commonly used solder paste for SMT reflow applications, and 96.5Sn/3.5Ag (by weight), a lead‐free solder alloy, was examined during thermal cycling. Based on these observations, the rate of crack propagation was estimated. Microstructural changes in the solder during thermal cycling were also studied.