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Analytic approximations are presented for the response of buckling-mode electrothermal actuators with very slender beams with a width-to-length ratio of W/L≤0.001 of the type found in nanoelectromechanical systems (NEMS). The results are found as closed-form solutions to the Euler beam bending theory rather than by an iterative numerical solution or a time-consuming finite element analysis. Expressions for transverse deflections and stiffness are presented for actuators with the common raised cosine and chevron pre-buckled shapes. The approximations are valid when the effects of bending dominate over those of axial compression. A few higher-order approximations are also presented for less slender beams with 0.001≤W/L≤0.01.

Sidewall transfer lithography (STL) is demonstrated as a method for parallel fabrication of 2D nanostructured cellular solids in single-crystal silicon. The linear mechanical properties of four lattices (perfect and defected diamond; singly and doubly periodic honeycomb) with low effective Young's moduli and effective Poisson's ratio ranging from positive to negative are modelled using analytic theory and the matrix stiffness method with an emphasis on boundary effects. The lattices are fabricated with a minimum feature size of 100 nm and an aspect ratio of 40:1 using single- and double-level STL and deep reactive ion etching of bonded silicon-on-insulator. Nanoelectromechanical systems (NEMS) containing cellular materials are used to demonstrate stretching, bending and brittle fracture. Predicted edge effects are observed, theoretical values of Poisson's ratio are verified and failure patterns are described.

Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation

A batch fabrication process for nanoelectromechanical systems (NEMS) based on sidewall transfer lithography (STL) is demonstrated. The STL is used to form nanoscale flexible silicon suspensions entirely by conventional photolithography. A two-step process for combining microscale and nanoscale features is used to fabricate double-ended and single-ended electrothermal actuators with a minimum feature width of 100 nm and an aspect ratio of 40:1. All devices are fabricated by deep reactive ion etching in 4.5-μm-thick silicon using bonded silicon-on-insulator material. The process could allow low cost fabrication of nanoscale sensors and actuators.

Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctions of comparable dimensions. Further development in nanoelectronics depends on the capability to generate mesoscopic structures and interfacing these with complementary metal–oxide–semiconductor devices in a single system. The authors employ a combination of two novel methods of fabricating room temperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-N SPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation. The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist (Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637, 76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because of the extremely low resist thickness, which limits the etching depth. The authors developed a computer simulation code to simulate the reactive ion etching at cryogenic temperatures (−120 °C). In this article, the authors present the alliance of all these technologies used for the manufacturing of SETs capable to operate at room temperatures.

The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature single-electron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip- and the laser-writing positions were determined in-situ with the scanning probe. We demonstrate < 100 nm precision in the registration between the high resolution and high throughput lithographies. The SET devices were fabricated on degenerately doped n-type > 1020/cm3 silicon on insulator (SOI) chips using a CMOS compatible geometric oxidation process. The characteristics of the three devices investigated were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO2, forming quantum dots (QDs). The small size and strong localisation of electrons on the QDs facilitated SET operation even at room temperature. Temperature measurements showed that in the range 300 K > T > ~100 K, the current flow was thermally activated but at < 100 K, it was dominated by tunnelling.