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The proliferation of artificial intelligence (AI) has opened up new avenues for the modeling of power electronics with ultra-fast transient responses, such as wide-bandgap (WBG) devices. This paper highlights the significance of ultrafast transient device-level hardware emulation for the DC railway microgrid (DRM) in real-time. To this end, the proposed approach partitions the DRM power system by transmission line method (TLM) and employs gated recurrent unit (GRU) and electromagnetic transient (EMT) modeling techniques for system-level subsystems. Meanwhile, for WBG devices, gallium nitride (GaN) high electron mobility transistors (HEMT) and silicon carbide (SiC) insulated gate bipolar transistors (IGBT) are modeled using a novel physical feature neuron network (PFNN), which offers high flexibility with a variable time-step (as low as 1ns), thereby improving the accuracy, efficiency and accelerating the emulation on the field-programmable gate array (FPGA). The effectiveness of the proposed approach is confirmed by comparing the emulation results with offline simulation results obtained from PSCAD/EMTDC® for system-level and SaberRD® for device-level transients. The proposed PFNN approach provides strong versatility, ultra-fast transient emulation capability, and significantly improved accuracy, which bodes well for the future of power electronics device-level emulation.

To mitigate the data transmission burden, an new memory event-trigger scheme is developed for the load frequency control (LFC) of multi-area networked power systems with the integration of various new energy sources. Hinfinitystability criteria under less conservative conditions are established by utilizing an improved Lyapunov stability theory and a second-order Bessel-Legendre (B-L) inequality for the LFC power system using the presented memory event-trigger scheme. Simulation on a two-area LFC system and IEEE-39 bus station test system are performed to validate the proposed method.

Accurate tracking the dynamics of power system plays a significant role in its reliability, resilience and security. To achieve the reliable and precise estimation results, many advanced estimation methods have been developed. However, most of them are aiming at filtering the measurement noise, while the adverse affect of partial measurement missing is rarely taken into account. To deal with this issue, a discrete distribution in the interval [0,1] is introduced to depict mechanism of partial measurement data loss that caused by the sensor failure. Then, a resilient fault tolerant extended Kalman filter (FTEKF) is designed in the recursive filter framework. Eventually, extensive simulations are carried on the different scale test systems. Numerical experimental results illustrate that the resilience and robustness of the proposed fault tolerant EKF method against partial measurement data loss.

Maritime industries desire high speed and reliability, low lifespan cost, and environmental impact shipping for transportation. Compared to highly congested land shipments and high-cost air freight, all-electric ship (AES) can reduce the lifespan energy consumption and transport a considerable freight volume at a lower rate. Recently, the medium voltage DC (MVDC) topology, recommended by IEEE standard, pushes the AES to the next stage in considering space and weight constraints with the reduction of bulky transformers and simplified parallel connections. However, device-level modeling of this massive parallel MVDC-based ship-board microgrid (SBM) is challenging to both the state-of-the-art general-purpose compute unit and traditional electromagnetic transient (EMT) based emulation. With the rapid development of machine learning (ML) algorithm and its dedicated execution unit, accelerated parallel emulation becomes achievable in different levels of this paralleled connected SBM. Applying the ML-aided technique can help to improve the emulation execution efficiency and reduce the consumption of hardware resource on the field-programmable gate arrays (FPGAs). This work proposes a real-time hybrid ML-EMT based digital twin of the complete SBM at the subsystem-level and equipment-level with validated results from PSCAD/EMTDC, and device-level with validated results from SaberRD.

In power system simulation, the mathematical solution methods are typically regarded as pure numerical operations, which are independent of the circuit principles. In this letter, it is demonstrated that the computational procedures in the commonly used numerical solution methods for circuit equations are essentially equivalent to the basic principles of electricity. The computational procedures of the representative Gaussian elimination based solution methods (including GE and pivoting method for sparsity of GE/LU) are comprehensively analyzed and their deep relationships with the circuit principles are revealed: the computation process of these mathematics based numerical solution methods can be completely explained using circuit principles. The interesting findings could help understand the computational process of solution methods from the circuit perspective, which may also guide the design of new circuit solution methods.

Modular multi-level converters (MMCs) are a mainstay in many HVDC transmission projects worldwide. Half-bridge MMC (HB-MMC) is mostly used in the current project. The large capacitor of sub modules (SMs) is often required in MMC to ensure the low voltage ripple. Here, the three-stage switching MMC (TSS-MMC) topology is proposed, which can greatly reduce the capacitor voltage ripple of SMs by dynamically adjusting the position of inductance on the upper and down bridge arms. The principle of reducing capacitor voltage ripple based on equal capacitance theory is introduced. The selection of the inductance value of each part in TSS-MMC is introduced. The start-up process strategy, capacitor voltage ripple reduction strategy in steady-state operation, and DC fault ride-through strategy of TSS-MMC are proposed. The effectiveness and engineering practicability of the proposed TSS-MMC is verified by transient simulation program built on PSCAD/EMTDC. The simulation results show that compared with MMC with circulating current suppressing controller (CCSC), it can effectively reduce the capacitor voltage ripple by over 50%. Furthermore, the total used inductance of TSS-MMC can also be reduced. A comprehensive assessment of TSS-MMC is also carried out.