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$400 Camera Panasonic Lumix DMC-LX5 The Panasonic Lumix DMC-LX5 combines a fast F2.0 Lens with Lightning-quick focusing, and it tops the manual exposure controls that most advanced point-and-shoot cameras offer [...]

Studios that have ventured into the 3D stereoscopic business see a lot of potential. More and more newly-produced content is seeing 3D release, including animated features, which has become somewhat [...]

To resolve the issue that a vast majority of time is spent on design and maintenance of new customized user interface in the development of digital TV system software, we propose TVSkin user interface, an architecture to be applied to the design of user interface software. With TVSkin user interface, there is no need to modify any of the programming codes, in order to make additions or changes to the user interface of a digital TV system. Therefore, the whole cycle of the product development can be shortened. This will make the design of a customized digital TV user interface and the replacement of its mechanism as easy as in the case of a popular skin-able user interface of a desktop application. In this way, a user interlace can be used more than once (1). Index Terms--Digital TV, User Interface, XML

In this paper we provide a system design method to solve the problem of developing a miniaturized portable digital TV set. For such a portable device it is very important to reduce its power consumption and extend its operation time as its battery is the only power source in the system. The hardware circuitry, therefore, must be relatively compact to be in accord with the high integration of the system-on-chip (SOC) and the proper selection of key components. Not only miniaturization can be realized but also cost and power dissipation of the system can be decreased. Whether the implementation can be achieved also depends on antenna efficiency and DVB-T receiver performance. Therefore it is vital to select the right radio frequency architecture, which affects both the signal reception and the power consumption. Based on the demands mentioned above we have chosen single a conversion architecture for the receiver. Furthermore, our design has a better performance than earlier designs because of the use of a shielding case and the appropriate filtering of power ripples. We implement the built-in spiral antenna body by means of the printed circuit board which is low-cost, wideband, small-sized, low-profile, and omnidirectional. Moreover, a heat sink conducts the heat outward and prevents overheating, thus ensuring operational safety (1). Index Terms--Digital Video Broadcasting--Terrestrial (DVB-T), Portable Digital TV, Power Consumption, Spiral Antenna, Receiver.

These A 3-band DTV tuner IC for DVB-C is designed in 0.25-pm CMOS process in this paper. The IC integrates not only mixer, PLL, but also an IF variable-gain amplifier. The mixer is based on Gilbert cell, and a transconductance linearization scheme is adopted to realize the highly linear, wide-range CMOS IF variable-gain amplifier with exponential gain control. A novel analog automatic amplitude controller based on charge-pump is proposed to stabilize performance across the 900-MHz tuning range without degrading the phase noise of VCO. An improved dual-module prescaler has wideband high input sensitivity. With 3.3V supply voltage, the measurements show that the mixer has voltage gain of 35 dB, the variable-gain amplifier provides continuous gain control range of 40dB, a C/IM3 of 61.2 dBc at 1-V peak-to-peak output, and the phase noise is below -82dBc/Hz at the 10 kHz offset frequency within the whole tuning range. The STB based on the designed IC has received cable DTV clearly. Index Terms--Tuner IC, CMOS PLL, VGA, DVB-C Receiver.

This paper proposes a structure-oriented multidirectional Sigma filter for additive white Gaussian noise in digital TV signals. Filtering is restricted to homogeneous directions to reduce blurring by analyzing local structure using directional second derivatives. The proposed filter improves the Sigma estimate of denoised pixels by imposing a homogeneity constraint on the noise-adaptive selection of estimation pixels by the Sigma filter. It achieves noise-reduction gains of up to 4.8 dB Peak-Signal-to-Noise Ratio (PSNR) in real-time. The block size, shape and coefficients of the filter are adapted to both structure and noise level. The goal is to optimize the filter with regard to noise-reduction gain and structure preservation. A possible hardware-oriented design of the proposed filter is also presented. To show the effectiveness of the proposed method, comparisons between the proposed Sigma filter and referenced Sigma filters in terms of the PSNR gain and the modulation transfer function (MTF) are shown. Results show that the proposed method achieves a higher PSNR gain and contrast transfer ratio than referenced Sigma filters. Index Terms--Real-time noise filters, Sigma filter, spatial multi-directional filters, structure preservation, digital TV noise

This paper presents a new architecture for liquid crystal display television (LCD TV), intelligent LCD (i-LCD), which enables communication between the image processing board and the LCD panel. This allows the image processing board to change key parameters in real time, which are necessary for full LCD panel functionality, i-LCD has a serial digital interface just like a communication channel where all the circuits are connected to a digital interface. Examples of two new circuits for i-LCD are found here,' they generate a common electrode voltage (Vcom) and gamma reference voltages. Both Vcom and the gamma voltages affect the long term operation of LCD TV panels and can be used to eliminate panel-to-panel color difference. An automatic optimization system is presented with proven automatic Vcom and gamma voltage tuning times of 0.35s and 4s, respectively. Hence, automatically optimized high quality LCD panels can be implemented in LCD TV. Other applications of i-LCD are also discussed. (1) Index Terms--liquid crystal display television, digital interface, flicker, gamma curve, automatic adjustment.

Digital television middleware is a new research field of digital television. It is a software platform in the receiver of digital television broadcasting. It allows various set-top boxes to be used in digital television broadcasting network. This paper addresses the structure of digital television middleware system. The security sub-system is investigated and analyzed. The fundamental principles of construction and operation of the security sub-system accord with Chinese digital television middleware standards are presented. The security sub-system is designed and implemented by using encryption techniques. It has been used in real environment of interactive DTV system. Index Terms--DTV, STB, middleware, security, signature

There's never been more variety in TV types, sizes, and shapes than there is right now. If you'd love a flat-panel set that's only a few inches thick, an LCD [...]

The TV systems are currently undergoing digitalization and will become more multifunctional, leading to more complex TV operation. This paper introduces a new interface system for a digital TV control utilizing speech recognition. A speech recognition system, which is designed for home use, especially for Digital TV, must be simple and robust to speaker variations caused by generation diversity. The remote control must enable an instant functionality and is equipped with a built-in microphone and press-talk switch. The whole system utilizes speaker adaptation techniques for assisting the user. Index Terms--digital TV, speaker adaptation, speech recognition, user interface.

For the moment, India and Iraq are set-top box hot spots du jour. In India, demand is driven by the government's determination to push through conditional access regulations no-one wants [...]

AS THE CITY OF NEW YORK MARKS THE ONE-YEAR ANNIVERSARY OF THE TERRORIST attacks of Sept. 11, its citizens and politicians continue to struggle with future plans for the World [...]

RANDALL P. DARK President/CEO HD Vision www.hdvision.com Dallas STRENGTHS The world has changed dramatically with the events of 9-11. Historically, in times of conflict the entertainment industry has always been [...]

A DVD-S and DSS compliant single-chip CMOS device for QPSK satellite digital TV reception has been developed recently. This paper presents the chip architecture and details on the performance under different channel conditions.

This paper describes a single ASIC chip that demodulates and decodes vestigial side band (VSB) digital TV signals. The VSB IC has been implemented for the receiver based on the ATSC digital TV standard[1[. It features fast digital carrier recovery and robust channel equalization. The IC is fabricated with 0.35 mu m CMOS technology with 3 metal layers. It can be applied to both modes of signal reception 8 VSB for terrestrial broadcast and 16 VSB for cable transmission.

In this paper, a single chip HDTV decoder is presented which drastically cut down the cost of HDTV receiver. The cost reduction is achieved by integration of system parser, down-converting video decoder, and multi-mode audio decoder. System designers can also benefit from the features of our decoder which requires only 4 Mbytes of SDRAMs (synchronous DRAM) for decoding HDTV signal and various system-level functions such as IEEE 1394 bus interface, I(super 2)C bus controller and on-chip clock recovery function.

This paper presents a state-of-the-art low-cost DTV decoding scheme. This novel approach consists of a combination of down-scaling and embedded compression within the MPEG decoding loop, and can save both memory and memory bandwidth. Experimental results demonstrate that this approach efficiently preserves the quality of the output low resolution image.

This paper introduces a transmission scheme for ISDB-T, and proposes a soft decision decoding technique for ISDB-T receivers to improve reception performance under multipath distortion and interference from analog television signals.

In this paper we present and analyze a full-digital decision-directed symbol timing recovery circuit based on the double-sampling maximum-likelihood estimator. Intended for the ATSC digital TV system, the proposed scheme works independently of the segment synchronization by extracting timing information from the randomized data symbols even in the extremely small roll-off case. With the proposed method we get not only quick synchronization, but also robust timing recovery with reduced timing jitter compared to the conventional correlation method [1]. The simulation is performed using the 8-level PAM signal, and evaluated in terms of the steady-state timing jitter under AWGN and multi path ghost channels. Additionally, initial timing acquisition and segment synchronization performance are also shown.

Completely digital symbol timing recovery architectures have advantages over the conventional mixed analog and digital approach, such as ease of system integration (especially for VLSI implementations) and flexible sampling rates. This paper is split into two main parts. The first part describes a digital symbol timing recovery architecture designed for digital television (DTV) receivers and also presents the associated design tradeoffs. The second part discusses an important aspect of the VLSI implementation of the architecture, which is the design and verification of the system clocking scheme.

The paper presents the development of an FEC decoder for ATSC digital TV. An FEC encoder/decoder system has been first built up for studying the performance of the FEC decoder and also for providing testing vectors for the architecture design. The architecture of the FEC decoder, including trellis decoder, de-interleaver, Reed-Solomon (RS) decoder and de-randomizer is then designed. The decoder has been prototyped in FPGAs and verified using an FPGA board. The FEC decoder can achieve the threshold of visibility (TOV) at 14.9 dB and 18.8 dB in the cases without and with NTSC rejection filter respectively.

We report a new unsynchronized timing recovery method designed for receiving digital TV signals modulated in 256QAM, QPSK and VSB format. The new method includes a simplified and efficient interpolator design, and a fast converging PLL. It can be used for fixed rate as well as variable rate applications. The algorithm was developed using SPW, and implemented using an FPGA-based prototype board using real data[1].

In the age of digital multimedia, demand is bound to rise for a television Home Server for integrated services which automatically records favorite programs so that users can watch them at any time. We have developed a hierarchical storage management system (HSMS) as the architecture for developing a high-speed Home Server with very large capacity. This paper first describes the required specifications and memory construction of the Home Server and then proposes a model of the new HSMS. Also described are its element technologies and an experimental Home Server system, and the results of experiments conducted to test its performance.

This year, over-the-air digital TV (DTV) is set to begin broadcasting in the United States and Europe. DTV standards allow new set-top and converter boxes to take advantage of better [...]

This paper introduces Rapid Prototyping of a complex system and the difficulties that appear when a real-time prototype of such a system is approached. These concepts are applied to the construction of a test modem for Terrestrial Broadcasting of Digital Television, in which Orthogonal Frequency Division Multiplexing (OFDM) is the transmission technique. The possibility of reducing the number of sub-carriers in the OFDM signal and obtaining enough information about the system performance in hostile environments (multipath, phase noise, non-linear, ...) is considered and discarded. As a conclusion, a non-real time prototype is presented which allows one to optimize parameters, verify the possibility of implementation and evaluate subjective qualities.

TV stations expect to spend millions in the coming years to broadcast a second, digital TV signal, but before they do they'd like to know how they are going to [...]

All of the processing necessary to convert an analog video signal into a digital component stream have been Integrated onto a single 68-pin IC. Processing features include nonlinear scaling which allows to switch between 4:3 and 16:9 applications under software control.

This paper describes a single chip demodulator for 64/256 QAM targeted to digital cable transmission applications. This chip incorporates specific novel functionality to mitigate channel impairments typical of cable transmission systems and consumer grade tuners.

This paper describes optimized digital NTSC picture coding in which circuit and system configurations are simplified by lowering the sampling frequency and quantizing level. The sampling frequency and quantizing level are determined based on the subjective evaluation of the reproduced picture quality. In accordance with the result of the subjective evaluation, the digital NTSC picture containing one third of information as compared with that of the normal digital NTSC picture was found to be satisfactory. Although the digital NTSC picture coding system normally uses a sampling frequency of 4x fsc (fsc: the color subcarrier frequency of the NTSC system) with a quantizing level of 8 bits, the subjective evaluation leads to the result of a sampling frequency of 2.28x fsc with a quantizing level of 5 bits.

This paper proposes a new digital convergence system which calculates the compensation data based on the 2nd and 4th degree Lagrange interpolating polynomials, using a real time chip, and it requires only a small memory space. Experimental results by actual implementation showed that the proposed system is much more efficient than conventional systems.

A DVB compliant chipset for QAM reception on cable was developed. It consists of two IC's, a down converter and an integrated QAM processor/FEC device including ADC, digital demodulation, equalization, clock and carrier recovery, and a forward error correction.

A QPSK chipset applicable for DVB signals on satellite is described. It consists of two IC's, a bipolar I/Q demodulator with on-chip AGC and a MOS QPSK processor device with ADC, clock and carrier recovery Viterbi- and RS forward error correction.

A celebrity investor, a hot technology, a seasoned founder: Home Team Advantage looks as if it has everything going for it - except customers Some start-ups are predicated on simple [...]

The technology and capability of television post-production systems has changed so completely over the past five years that television businesses should thoroughly review the role post-production plays in their operations. [...]

We audition six PC-based digital video boards that will put the media in your multimedia productions Introduction by Lou Wallace - Review Board Test Development and Testing by Patrick Lyons […]

A BEHIND-THE-SCENES look at Tv postproduction reveals a need for speed--and a definite push toward going tapeless sooner rather than later. The CW comedy 'Everybody Hates Chris' shoots with the [...]