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Typical visitor access apps are usually passive/manual. The security guards in highly populated communities have to verify the identity of the visitors every single time, be it the residents or new people. This process is also time-consuming. Availability of the resident is also essential to approve the entry. VISITOR ACCESS is a better substitute for the regular visitor access systems. The process starts with choosing the house number and the name initially. When there is a known person, the visitor is verified, recognized, and approved to enter. If the visitor is unknown, he or she is asked to enter a few more details, which are sent to the resident’s mobile. A message is sent to the visitor’s mobile regarding the approval status to deal with the case of multiple visitors. Open CV is used to verify the identity of the visitors using face recognition, and the app acts as an interface between the users and the system.

In this script temperature analysis on a Hybrid double gate Junctionless transistor with gate engineering has been investigated to improve short-channel effects and gate controllability. The comparative analysis of the proposed device is done by varying the temperature in the range from 200 K to 500 K. The Hybrid Junctionless double gate transistor device at low temperature has provided a Subthreshold Swing of 39.59 mV/decade which is close to less than two-thirds of the ideal value of 60 mV/decade, DIBL at room temperature is found to be 4.21 mV/V. The off current is found as 4.879 x 10-19 A/µm and the switching ratio is very high obtained as 1.563 x 1015. Additionally, the impact of variations in temperature on surface potential, electric field, and electron velocity is also studied. It is found that the electron velocity becomes double as we move from 500 K to 200 K and a very high peak overshoot in electric field is observed at the channel drain interface. Also, the proposed device at room temperature provides nearly 28 % improvement in Subthreshold Swing and 93.42 % improvement in DIBL, and the minimum surface potential is very low then the generic Junctionless double gate transistor. [ABSTRACT FROM AUTHOR]

In the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance. [ABSTRACT FROM AUTHOR]

In this paper, we have proposed the precise model of coaxial TGVs (CTGVs) which consists of ground-signal signal-ground (GSSG) TGVs. An equivalent electrical model of CTGVs is established and the partial element equivalent circuit (PEEC) technique is used to extract the frequency-dependent impedance parameters. In CTGVs, multi-walled carbon nanotubes (MWCNT) and copper is used as filler material in inner and outer layer. Resistance and inductance of CTGVs is calculated using the PEEC technique for different filler materials. The insertion loss (S21) of CTGVs is determined using the HFSS simulations and is compared analytically in differential mode configurations. S21 is calculated for various geometrical parameters of MWCNT-based CTGVs such as diameter of TGV, pitch between CTGV pair, as well as material properties such as permittivity of SiO2 and benzocyclobutene (BCB) polymers. It is established that MWCNT based CTGV shows improved insertion loss because the conductivity of MWCNT is higher in comparison to copper. [ABSTRACT FROM AUTHOR]

A novel hybrid double gate junctionless transistor with gate engineering using a dual gate oxide stack has been proposed to improve short-channel effects and gate controllability for digital applications. The performance analysis and comparison of the proposed device with a DGLK junctionless transistor has been reported, hybrid Junctionless double gate transistor device has provided SS 61.4 mV/decade which is close to the ideal value of 60 mV/decade and 27.91% improvement, DIBL of 7.368 mV/V with 88.487% improvement, off current is 35.6 fA/µm, which is nearly 1.6 x10-6 times less and very high switching ratio of 1.648x 1010 which is 5.455 x106 times higher than junctionless double gate transistor. Also, the effect of variations in gate dielectric, spacer length has been studied. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of high-performance N-bit digital comparators for use in modern digital systems. Digital comparators are fundamental building blocks in many electronic systems, performing the critical task of comparing two digital values and generating an output indicating their relative magnitudes. For implementing N-bit digital comparator a new design for an 8T EX-OR-NOR cell with full rail-to-rail output swing has been proposed. The proposed EX-OR-NOR cell is based on the hybrid circuit utilizing CMOS inverter and transmission gate logics, which thereby uses less power and minimizes propagation delay. Thus, a high-speed N-bit digital comparator design is accomplished using the proposed 8T EX-OR-NOR cell. In the present work 4-bit to 32-bit digital comparators are designed and implemented using the proposed circuitry. All the circuits are designed using Cadence electronic design automation (EDA) Virtuoso Design Environment for 180nm CMOS technology node. The outcomes are evaluated and verified with the comparator designs reported in the literature. The proposed modified N-bit digital comparators provide an excellent combination of speed, power consumption, and accuracy, making them a promising solution for modern digital electronics systems. [ABSTRACT FROM AUTHOR]