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Traditional charge pumping (CP) technique relies on trap-assisted recombination from the source/drain to the body contact to characterize interface trap density ( ${N}_{\text {it}}$ ) of classical bulk MOSFETs. A variant of the technique called single pulse CP (SPCP) allows interface trap characterization even if the bulk contact is absent, as in silicon-on-insulator (SOI) MOSFET. Unfortunately, neither technique is useful for devices with source-body-tied (SBT) and inhomogeneous channel doping profile, as in lateral diffused MOS (LDMOS) power transistors. Here, we propose a generalization of the CP/SPCP techniques, called Super SPCP ( $\text{S}^{{2}}$ PCP), to extract position-resolved localized degradations ( ${\Delta {N}}_{\text {it}}$ ) in an SBT LDMOS. Careful TCAD modeling and experimental characterizations demonstrate the effectiveness of the proposed approach. Our analysis provides deep insights into the physics of the SPCP technique, demonstrating that the approach can be used to characterize a variety of transistors with nontraditional doping profiles and contact configurations.

Molding compounds (MCs) have been used extensively as an encapsulation material for integrated circuits, however, MCs are susceptible to moisture and charge spreading over time. The increase in dissipation factor due to the increase of parasitic electrical conductivity ({\sigma}) and the decrease in dielectric strength (E_MC^Crit) restrict their applications. Thus, a fundamental understanding of moisture transport will suggest strategies to suppress moisture diffusion and broaden their applications. In this paper, we 1) propose a generalized effective medium and solubility (GEMS) Langmuir model to quantify water uptake as a function of filler configuration and relative humidity; 2) investigate the dominant impact of reacted-water on {\sigma} through numerical simulations, mass-uptake, and DC conductivity measurements; 3) investigate electric field distribution to explain how moisture ingress reduces E_MC^Crit; and finally 4) optimize the filler configuration to lower the dissipation factor, and enhance E_MC^Crit. The GEMS-Langmuir model can be used for any application (e.g., photovoltaics, biosensors) where moisture diffusion leads to reliability challenges., Comment: 22 pages, 6 figures, Elsevier journal format

Since the 1970s, LDMOS transistors have been used in a variety of applications because of their versatility and monolithic integration with CMOS logic. Despite the advantages, interface defects (N IT ) generation due to Hot Carrier Degradation (HCD) has been a persistent reliability challenge for LDMOS transistors. Unfortunately, neither classical charge pumping nor single-pulse charge pumping techniques can be used to locate/quantify N IT in a source-body-tied LDMOS configuration. Here we: i) identify the multiple hotspots of HCD in an LDMOS using experimentally validated TCAD simulations; ii) introduce and implement a TCAD-enabled novel charge pumping technique to probe region-specific interface states in a source-body-tied (SBT) LDMOS; and iii) develop a unified multi-hotspot HCD model to interpret the degradation kinetics in power transistors. The analysis provides deep insights into the HCD in an LDMOS and the generalized charge pumping technique can be used to map interface states in a variety of transistors with non-traditional doping and contact configurations.

Although the CMOS-compatible Laterally Diffused MOSFET (LDMOS) is widely used in various applications as a versatile and efficient power electronic device, its hot carrier degradation (HCD) remains a persistent and important design challenge. None of the classical HCD models apply, because the geometric and doping complexities of the channel and drift regions create multiple hotspots with bias-dependent hot carrier injection into the oxide. To address these challenges, here we: 1) propose a novel geometrical partition of the LDMOS and represent each part by a TCAD-calibrated and experimentally validated tandem-FET compact model; 2) use the new compact model to propose an ‘ I − V spectroscopy’ methodology to deconvolve mobility and threshold degradation in the channel and the drift regions; 3) separate the degradation in the two regions by postprocessing measured I-V curves; 4) demonstrate that ΔV th determined by classical techniques, e.g., constant current (CC) or maximum transconductance (Gmmax), are contaminated by mobility degradation and must be corrected by the proposed technique for accurate lifetime projection.

The properties of different molding-compound materials with high filler contents have been investigated in order to assess their electrical properties. The experimental part of the present work has been focused on dielectric spectroscopy and steady-state conduction measurements. The results have been used to investigate the electrical properties of the materials at different frequencies, temperatures and electric fields. Differences in the relaxation kinetics with increasing filler content have been found, which can be ascribed to the larger interface regions between the filler particles. In addition, the extracted conductivities show a hopping transport and different activation energies on the temperature range from 20 °C to 190 °C.

Unlike traditional logic transistors, hot carrier degradation (HCD) in power transistors involves simultaneous and potentially correlated degradation in multiple regions. One must deconvolve and characterize the voltage- and temperature-dependence of these region-specific degradations to develop a predictive HCD model of power transistors. Unfortunately, power transistors' doping and geometrical complexities make it challenging to use traditional defect-profiling techniques, such as charge-pumping or gated-diode methods. This Letter uses a physics-based tandem-FET model of an Laterally Diffused MOS (LDMOS) transistor to develop a “three-point I–V spectroscopy” technique that uses the time-evolution of three critical points of the measured I–V characteristics to extract mobility and threshold voltage degradations in the channel and drift regions. This innovative approach should generalize to other configurations of the LDMOS transistor as well.

High electric fields and temperatures in high-voltage ICs (HV-ICs) can induce charge transport phenomena in the encapsulation material leading to reliability test failures. In this paper, the resistivity of epoxy-based resins with insulating microfiller weight fraction exceeding 70% has been experimentally and theoretically investigated for the first time. Electrical conductivity has been measured at high temperature (150 °C) using both dielectric spectroscopy analysis on bulk samples and charge-spreading characterizations on a dedicated test chip with integrated charge sensors. The use of a charge sensor close to the internal HV metallization leads to results more pertinent with the active area of HV-ICs. Remarkably, both experiments show an unexpected increase and a significant variability of the electrical conductivity as the microfiller fraction is increased. The strong correlation between bulk and lateral experiments clearly indicates that those features should be attributed to the bulk material. Numerical simulations of diffusion phenomenon in mold structures with random arrangements of spherical microfillers demonstrate that the conductivity increase with filler content can be ascribed to the role of the epoxy/filler interfaces.

This paper studies the impact of self-heating effects in DC-based Hot Carrier Injection (HCI) modeling in power LDMOS devices. Continuous and large power consumption under the on-state DC stress can result in substantial increase in device temperature, which potentially causes non-negligible error in the HCI modeling. The issue is systematically investigated and verified through various approaches such as comparison of HCI degradation between the devices with different voltage ratings and finger widths, junction temperature estimation with 3D thermal simulation, and pulse-based stress modeling. In addition, it is shown that reliability projection methodology based on the actual circuit waveforms can be more immune to the potential errors caused by the self-heating effect in the conventional DC-based modeling.

Stacked intermetal dielectrics grown by a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique are widely used as a capacitive voltage divider to integrate low and high power ICs. The voltage-divider must sustain multi-kV operation for years in harsh (hot and humid) environment. Therefore, a fundamental understanding of the degradation mechanisms of the dielectric is an essential prerequisite for its safe operation. While the reliability of PECVD oxides has been extensively studied, the reliability of stacked oxides, with numerous chemically and mechanically polished (CMP) interfaces, is not fully understood. In fact, the dielectric reliability would differ dramatically if the stack behaves as a single thick capacitor vs. if CMP-damaged interfaces render the stack into a set of capacitors connected in series. In this paper, we use a wide range of the stacked intermetal dielectric (= 1∼20 μτη) to study their Time-dependent dielectric breakdown (TDDB) degradation mechanism. Our results demonstrate that the stacked dielectric do behave as a single unit, but unlike conventional TDDB in submicron gate oxide, the TDDB of stacked dielectrics is determined by impact ionization and charge trapping. We explored the degradation mechanism in detail through experiments and simulation; the results are embedded in an acceleration model that can be used to predict TDDB lifetime at arbitrary operating conditions.

Ferroelectric materials are the most common example of a Landau structure, defined as a system having an atom/mass moving in a double-well energy landscape. These materials have applications in memories, actuators, low power logic transistors, and so on. For a bipolar ac signal typical in most of the applications, one suspects that the repeated roller coaster shuttling of the moving atoms located microscopically at the domain walls could lead to bond dissociation, suggesting a new channel for defect generation with no classical counterpart. Here, we demonstrate that once the bipolar pulses initiate transfer of atoms between the energy pockets, the transient overshoot away from their equilibrium positions (hot atoms) leads to significant increase in defect generation. We interpret the degradation theoretically and demonstrate a set of soft-switching schemes to control the hot atom damage and to improve the device lifetime dramatically. The damage mechanism should be generic in other Landau structures, such as microelectromechanical systems, nonvolatile memories, and analogous control strategies should improve the lifetime of all such bistable devices.

Inorganic fillers, such as fused silica or organic clay, help tailor/co-optimize the mechanical toughness, thermal conductivity, and moisture diffusivity of polymer mold compounds used to package microelectronic integrated circuits. Despite long history and wide-spread current use, the optimization of filler-infused composites is generally empirical and therefore time-consuming. A physics-based predictive modeling will improve application-specific design of composites that would offer optimum performance and reliability. As an illustrative example, in this paper, we develop a general theory of polymer composites that anticipates the suppression of moisture diffusion as a function of fill-fraction, size-dispersion, shape, and topology of filler nanoparticles. Our results show that the best performance is obtained by incorporation rod-shaped fillers, randomly closed packed at maximum density (∼60%). Our numerical results are succinctly captured by the analytical model based on generalized Maxwell Garnett effective medium theory. The analytical model can be used for initial optimization of mold compounds before large-scale numerical modeling is invoked and characterization experiments are designed.

A new self-consistent technique is proposed to simultaneously extract the density of interface traps (Dit) and flat-band voltages of MOS structures fabricated on technologically relevant high-mobility semiconductors with arbitrary combination of gate stacks. The technique is based on novel analysis of the low-frequency C–V measurement. The two major problems associated with the existing low-frequency C–V technique for arbitrary substrate/oxide combinations are resolved by (i) accurate calculation of the ideal semiconductor capacitance using a self-consistent, quantum–mechanical model including wave function penetration effect, and (ii) accurate determination of the flat-band voltage utilizing an iterative scheme. The proposed technique has been applied to extract Dit profiles of a number of MOS structures fabricated on III–V semiconductors like InGaAs (with ALD grown Al2O3 gate dielectric) and elemental semiconductors like Ge (with GeON gate dielectric). The advantages of the proposed technique have been demonstrated by comparing with Dit profiles extracted from other capacitor-based extraction methods.

A close analysis of the universality of OFF-state hot carrier degradation (HCI) in drain-extended transistors suggests that on-state HCI degradation should likewise be universal. In this paper, we confirm this hypothesis through an extensive set of experiments on drain-extended n-channel metal-oxide-semiconductor (DeNMOS) transistors and demonstrate that the underlying mechanism for both OFF- and ON-state degradation are essentially identical (even though the drain current differs by several orders of magnitude for the respective stress bias conditions). We show how this universality of ON- and OFF-state hot carrier degradations allows the use of short-term measurements to predict device lifetime under arbitrary operating conditions.

A theory of the current-ratio (CR) technique in uniform semiconductors, which is widely used to locate gate oxide breakdown (BD) spots in one dimension (i.e., distance from source or drain), is proposed and verified. The theory shows that the CR method is a special case of generalized van der Pauw technique and, as such, can easily be generalized to locate oxide BD spots in two dimensions. We develop the theoretical framework of this new class of BD-spot characterization techniques and then validate the theory by experiments. We conclude by discussing the implications of locating BD spots in two dimensions for reliability projections of ultrathin gate oxides.

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.

Recent advances in experimental techniques (on-the-fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale. Such measurements over wider temperature range (-25 degrees C to 145 degrees C, film thicknesses (1.2-2.2 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation. In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes.

Impact of gate dielectric processing [plasma and thermal nitridation, nitrogen total dose, effective oxide thickness (EOT)] on negative-bias temperature instability (NBTI) degradation and recovery is studied. The magnitude, field, and temperature dependence of NBTI is measured using no-delay IDLIN method and carefully compared to charge-pumping measurements. Plasma (thin and thick EOT) and thermal (thin EOT) oxynitrides show very similar temperature and time dependence of NBTI generation, which is identical to control oxides and is shown to be due to generation of interface traps. NBTI enhancement for oxynitride films is shown to be dependent on nitrogen concentration at the Si-SiO2 interface and plasma oxynitrides show lower NBTI compared to their thermal counterparts for same total nitrogen dose and EOT. Both fast and slow NBTI recovery components are shown to be due to recovery of generated interface traps. Recovery fraction reduces at lower EOT, while for similar EOT oxynitrides show lower recovery with-respect-to control oxides. NBTI generation and recovery is explained with the framework of reaction-diffusion model., © IEEE

This paper reviews the experimental and modeling efforts to understand the mechanism of Negative Bias Temperature Instability (NBTI) in p-MOSFETs, which is becoming a serious reliability concern for analog and digital CMOS circuits. Conditions for interface and bulk trap generation and their dependence onstress voltage and oxide field, temperature and time are discussed. The role of inversion layer holes, hot-holes and hot-electrons are also discussed. The recovery of generated damage and its bias, temperature and AC frequency dependence are discussed. The degradation and recovery is modeled using the standard Reaction-Diffusion theory, and some unique data scaling features are pointed out. The impact of gate-oxide nitridation is also reviewed.

Four molding-compound composites with different silica micro-filler size and concentration have been measured on top of dedicated IC test structures. The leakage current of charge sensors has been monitored under different high-voltage stress during charging/discharging transients occurring in the mold. Physical insight of space charge distribution at high electric field and temperature has been obtained by TCAD analysis. The role played by the encapsulation composition on the device-package interaction has been investigated via TCAD simulations of the HTRB test of a Single-RESURF LDMOS.

Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high Vgs biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative explanation of the dependence on frequency and duty cycle has been obtained using the new approach based on physical models. An extended analysis of the HCS degradation in a real switching application through a resistive load has been reported to gain an insight on the role played by the peak-HCS rates during the rising/falling edges.

We study OFF-state and sub-threshold degradation in scaled NMOS transistors and propose a unified channel current (I S ) and drain-to-source voltage (V DS ) dependent lifetime model for a wide range of bias conditions. The lifetime dependence on V DS suggests that degradation is limited by the maximum energy available for the channel electron in short channel transistors.

Two parameters - the distribution of failure times and the voltage dependence of defect generation - define IC lifetime limited by time-dependent dielectric breakdown (TDDB). While the physics of both parameters for uniformly stressed thin-gate dielectric are well known, we find that the corresponding parameters for asymmetric off-state TDDB are anomalous and cannot be understood by a simple application of the classical models. Here we report experimental and theoretical resolutions of the anomaly and show that, despite the complexity of the breakdown process, a simple charge-pumping measurement provides an unambiguous/effective/inexpensive monitor of the anomalous Weibull slopes and nontraditional voltage-acceleration factors for off-state TDDB.

The nature and composition of generated interface-trap (ΔNIT) in p-MOSFETs is studied as a function of hole energy. By observing the time dependence of generation during stress and the amount of recovery after stress, it is shown that ΔNIT is due to both broken ≡Si--H and ≡Si--O-- bonds, their ratio governed by hole energy. In the absence of hot holes ΔNIT is primarily composed of broken ≡Si--H, which show a lower power-law time exponent and a fraction of which anneal after stress. Additional ΔNIT is created in the presence of hot holes, which is due to broken ≡Si--O-- bonds. These traps show a much larger power-law time exponent, and they do not anneal after stress. These observations have important implications for lifetime prediction under negative bias temperature instability, Fowler-Nordheim, and hot carrier injection stress conditions., IEEE

It is not always practical to observe OFF-state drain-to-gate dielectric breakdown in power transistors due to the upper limit set to stress voltage by junction breakdown. In this paper we demonstrate that OFF-state breakdown in drain extended power transistors can be accelerated by increasing the channel current (IS) by biasing the transistor in sub-threshold. We also show that the charge pumping scaling factors along with observed breakdown times can be used to build an IS and VDG dependent model to extrapolate failure times at operating bias conditions.

We use a lateral scaling methodology based on the bond-dispersion model to develop a generalized hot carrier degradation model for cascoded NMOS transistors in power management applications. Spatial profiling of interface traps (N IT ) based on charge pumping measurements is used to identify damage regions responsible for V T and I DLIN degradation and to explain their time dependencies.

In this paper we have developed a model to obtain drain current (ID) degradation at all transistor operating modes (linear, saturation and sub-threshold) during NBTI stress based on threshold voltage (VT) and mobility (µ) degradation. This model provides a compact way to comprehend NBTI induced drain current degradation for transistors subject to multiple operating modes (e.g., dynamic voltage scaling, active/standby modes).

We develop a novel approach for hot carrier lifetime prediction based on the ‘universality of HCI degradation’ that not only generalizes the classical theory by obviating the measurement of I B , but also allows prediction of HCI lifetime over a broad range of technology nodes, bias conditions, and device geometries. We explain the shape of the degradation vs. time characteristic based on the energy distribution of the Si-O bonds, and we show, based on the bond-dispersion model, that the degradation shows similar features for both ON- and OFF-state bias conditions.

Through a combination of measurement techniques, we study the interface properties of In0.65Ga0.35As transistor with ALD deposited Al2O3 gate dielectric. We show that the interface trap density at In0.65Ga0.35As/Al2O3 interface can be relatively high, but the transistor still exhibits inversion characteristics. A detailed profiling of the interface traps shows that majority of the interface traps are donor-like, and explains the absence of Fermi level pinning in spite of the high interface trap density.

In this paper, we provide the first systematic and comprehensive analysis of off-state degradation in Drain-Extended PMOS transistors - an enabling input/output (I/O) component in many systems and a prototypical example of devices with correlated degradation (i.e., hot carrier damage leading to gate dielectric failure). We use a wide range of characterization tools (e.g., Charge-pumping and multi-frequency charge pumping to probe damage generation, IDLIN measurement for parametric degradation, current-ratio technique to locate breakdown spot, etc.) along with broad range of computational models (e.g., process, device, Monte Carlo models for hot-carrier profiling, asymmetric percolation for failure statistics, etc.) to carefully and systematically map the spatial and temporal dynamics of correlated trap generation in DePMOS transistors. Our key finding is that, despite the apparent complexity and randomness of the trap-generation process, appropriate scaling shows that the mechanics of trap generation is inherently universal. We use the universality to understand the parametric degradation and TDDB of DePMOS transistors and to perform lifetime projections from stress to operating conditions.

Through a combination of measurements techniques, we show that the generation of both interface and bulk traps during off-state stress in drain extended NMOS transistors are driven by the same physical mechanism and as such have similar time and voltage dependencies. We also show that the peak interface damage location (obtained from charge pumping measurement) along with asymmetric percolation model successfully interpret the observed Weibull slope of dielectric breakdown during off-state stress. Our analysis suggests the intriguing possibility of replacing time consuming off-state TDDB measurements by simple charge pumping analysis.

Negative bias temperature instability (NBTI) is studied in plasma (PNO) and thermal (TNO) Si-oxynitride devices having varying EOT. Threshold voltage shift (DeltaVT) and its field (EOX), temperature (T) and time (t) dependencies obtained from no-delay on-the-fly linear drain current (IDLIN) measurements are carefully compared to that obtained from charge pumping (CP). It is shown that thin and thick PNO and thin TNO devices show very similar NBTI behavior, which can primarily be attributed to generation of interface traps (DeltaNIT). Thicker TNO devices show different NBTI behavior, and can be attributed to additional contribution from hole trapping (DeltaNh) in pre-existing bulk traps. A physics based model is developed to explain the experimental results.

Recently several groups have used the reaction-diffusion (R-D) model with H2 diffusion in interpreting negative bias temperature Instability (NBTI) degradation. While the classical “H2 R-D” model can interpret long-term NBTI behavior, it is inconsistent with short-term stress data obtained by recently developed ultrafast measurements and widely used on-the-fly measurements. Moreover, experimental data from various techniques are not consistent with each other. Here, the authors show that the H2 R-D model must be generalized to consistently interpret NBTI at all time scales. The generalized model highlights the previously unappreciated role of time-zero delay in reconciling differences among the so-called delay-free on-the-fly measurements.

Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.

Off-state degradation in drain extended NMOS transistors is studied. It is shown that the damage is primarily due to Si-O bonds broken by hot carriers. These hot carriers are generated through impact ionization of surface band-to-band tunneling (BTBT) current. The resultant degradation is found to be universal, enabling reliability projections at lower stress voltages and based on shorter duration tests, than previously anticipated

A common framework for interface-trap (NIT) generation involving broken ≡Si-H and ≡Si-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress. Holes (from inversion layer for pMOSFET NBTI, from channel due to impact ionization, and from gate poly due to anode-hole injection or valence-band hole tunneling for nMOSFET HCI) break ≡Si-H bonds, whose time evolution is governed by either one-dimensional (NBTI or FN) or two-dimensional (HCI) reaction-diffusion models. Hot holes break ≡Si-O bonds during both FN and HCI stress. Power-law time exponent of NIT during stress and recovery of NIT after stress are governed by relative contribution of broken ≡Si-H and ≡Si-O bonds (determined by cold- and hot-hole densities) and have important implications for lifetime prediction under NBTI, FN, and HCI stress conditions., IEEE

Interface trap (NIT) generation and recovery due to broken ≡Si-H bonds at the Si/SiO2 interface is studied during and after hot carrier injection (HCI) stress and verified by a two-dimensional reaction-diffusion model. NIT generation and recovery characteristics do not correlate with channel hot electron (HE) density distribution (verified by Monte Carlo simulations). Anode hole injection, which is triggered by HE injection into the gate poly, and valence band hole tunneling, which is triggered for thinner oxides, must be invoked to properly explain experimental results. The observed hole-induced, not electron-induced, breaking of ≡Si-H bonds during HCI stress is also consistent with that for negative bias temperature instability stress., IEEE

The generation and recovery of interface traps (NIT) during and after hot carrier injection stress is evaluated by the recently proposed two-dimensional (2-D) reaction diffusion (R-D) model. The power law time exponent (n) of NIT generation as well as the magnitude of fractional and absolute recovery after the stress cannot be fully explained by considering only the spatial extent of broken ≡Si-H bonds, as is done by 2-D R-D model. Additional contribution due to broken ≡Si-O bonds also plays a major role in determining the overall NIT generation and recovery behavior., IEEE

Negative bias temperature instability (NBTI) is studied in ultrathin Si oxynitride (SiON) films made by thermal (TNO) and plasma (PNO) processes. Threshold voltage degradation (DeltaVT) and recovery during and after NBTI stress are explained by generation and recovery of interface traps (DeltaNIT)