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In this research paper, a Vertical Tunnel FET structure in the presence of a live metal strip & low dielectric constant material is designed and its performance metrics are analyzed in detail. A low dielectric SiO2 material is incorporated in the channel/drain region. Low work function live metal strip (Molybdenum) is placed in high-k dielectric HfO2 layer in source/channel region. The device is examined by the parameters Ioff, subthreshold swing, threshold voltage, and Ion/Ioff ratio. The introduction of a live metal strip in the dielectric layer nearer to the source-channel interface results in a minimum subthreshold slope and a good Ion/Ioff ratio. Low dielectric material at drain reduces Cgd-Miller capacitance. Both the SiO2 layer & low work function live strip show excellent leakage current reduction to 1.4 × 10-17 A/μm. The design provides a subthreshold swing of 5 mV/decade which is an excellent improvement in TFET, ON current of 1.00 × 10-5 A/μm, an Ion/Ioff ratio of 7.14 × 1011 and the threshold voltage of 0.28 V. [ABSTRACT FROM AUTHOR]

In the present paper, the linearly graded work function (LG-W) characteristics are explored by using binary metal alloy aσb1 – σ gate electrode composition in a high-k gate stack with a dielectric pocket in vertically aligned TFET (VTFET). The VTFET device is constructed using a binary metal alloy gate electrode with a linearly graded work function and an air pocket. The proposed structure performance metrics are evaluated and compared to the state-of-the-art. The integration of LG-W with gate-stack VTFET along with air pocket, namely SG-LG-VTFET with air pocket, reveals performance improvement via metrics such as device ON-current (ION), subthreshold swing (SS), transconductance (gm) as well as transconductance generation efficiency (TGE). SG-LG-VTFET with air pocket generates SS of 13.92 mV/dec. Further, the device exhibits a higher ION (3.6.10 – 5 A/µm) with an ION/IOFF ratio of 1012. Due to the inclusion of the LG-W and air pocket, a narrow band-bending is observed, thus resulting in higher tunneling and steeper SS. A high-k stacked dielectric material enhances the capacitive coupling. The performance of the device is compared with the VTFET device in the absence of a dielectric pocket. The dielectric pocket increases the electric field, which is a desirable phenomenon for increasing the ON-current. For future applications, the scaling in SS is further possible that can increase the electron tunneling rate. [ABSTRACT FROM AUTHOR]

In recent research, very large-scale integration (VLSI) design and its implementation plays a major role. It has been considered as compact and contains additional techniques. However, it undergoes security threats like differential power analysis (DPA) attacks, confidential information leakage, suspicious data insertion, brute force attacks, and other severe attacks. Hence, the cryptographic techniques that have been implemented to enhance the security level for VLSI devices is the focus of this survey. The symmetric cryptographic technique of advanced encryption standard (AES) is considered suitable for this security enhancement and it is an advanced encryption process, and so the intelligible data are transmitted in an unintelligible form to confuse the attackers and the data is securely transmitted without any interruption. Different techniques to implement the AES approaches in VLSI devices are analyzed. The dynamic S-box technique is also analyzed for key-dependent processes. The key-dependent S-box of block ciphers is more secure than a general fixed S-box. The strength of the cipher is increased by the usage of an S-box. A dynamic S-box, generated to be key-dependent and with a discrete logarithmic approach, enhanced the S-box nonlinearity. Several measures analyzed regarding security and complexity of nonlinear transformation of S-box improved. Hence, the AES algorithm with dynamic S-box makes the system dynamic, more nonlinear, and with an unbreakable architecture. In this review, it also identified that to implement nonlinear transformation in AES, an S-box component has been used. This survey has been provided as guidelines for VLSI architecture implementation in a more secure way with cryptographic algorithm of AES and a dynamic S-box. [ABSTRACT FROM AUTHOR]

Scaling has been instrumental in improving speed and power consumption. Moore's law insists on a constant periodic decrease in the size of devices. Gate dielectric engineering is one of the means to reduce the size of devices. This paper describes the simulation of the electrical characteristics of a reduced channel width and an increased dielectric thickness at the gate edges of a junctionless multigate transistor. The novelty of the work is the increased gate oxide thickness at the edges that reduces the leakage current. HfO2 is used as a dielectric material because thin SiO2 layer causes leakage through the gate oxide and into the channel. The excellent property of HfO2 is its high dielectric constant value (20-25), which is 4 to 6 times higher than of SiO2. In this work, the performance parameters of a double-gate junctionless FET, namely the threshold voltage (Vth), OFF-current, ON-current, ON-to-OFF current ratio, and subthreshold swing (SS), have been investigated for the gate work function window from 4.6 to 5.0 eV. In the work function window, optimal performance has been found for a gate work function of 4.9 eV. The proposed device has low IOFF and subthreshold swing when compared to conventional junctionless FET. This paper presents the simulation of a junctionless transistor using Atlas Silvaco TCAD tool. The device shows OFFcurrent of the order of 10 – 16 A/m, ON-to-OFF current ratio of the order of 1011 and subthreshold swing of 59.78 mV/dec. The device shows constant subthreshold swing for the work function range of 4.6 to 5.0 eV. The simulation results show that the proposed device is suitable for low power applications. [ABSTRACT FROM AUTHOR]

User data protection is a major problem in the technical world. To get critical data from people such as bank account, credit card details and passwords, fraudulent people use different techniques for their advantages. Misuse of user credentials affects many industry sectors day by day. The fraudulent practice where more people connected to a network revealing sensitive data of individual, group or a company of legitimate sources called phishing. The aids for the hackers are forged websites and emails which look similar as original. There are different anti-phishing methods are proposed which follows various methods, to protect users against phishing. Proposed technique has detection of phishing at various stages. It contains incoming mail analysis for its feature as well as source. If mail has link to webpage, that cautious webpage is checked for its legitimateness. It is examined by using two methods. For popular sites, webpage content is compared with content of known legitimate site. The second step is to find whether any cautious site is increasingly dependable on any related pages to calculate relationship strength indirectly or directly associated pages. To protect from phishing attacks, these techniques uses virtual passwords for logging into sites. [ABSTRACT FROM AUTHOR]