18 results on '"Devanathan, V.R."'
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2. New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation
3. ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs
4. Variation-Tolerant, Power-Safe Pattern Generation
5. Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs
6. Towards effective and compression-friendly test of memory interface logic
7. EOMP: an exactly once multicast protocol for distributed mobile systems
8. Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
9. On Power-profiling and Pattern Generation for Power-safe Scan Tests
10. A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
11. Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms
12. Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.
13. PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.
14. A framework for distributed and hierarchical design-for-test.
15. Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.
16. A framework for concurrency control in real-time distributed collaboration for mobile systems.
17. A framework for distributed and hierarchical design-for-test
18. Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs.
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