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International audience; Tin oxide SnO2 thin films were deposited by sol gel method on glass substrates. The as-deposited thin films were then annealed at 550 °C for different time durations (15, 30, 60 and 120 min). Structural and morphological investigations were carried out on all samples by X-ray diffraction method and atomic force microscopy while optical properties were obtained with UV–Visible spectrophotometer. XRD patterns reveals that the samples possess polycrystalline with rutile structure of SnO2 without any secondary phase. AFM image showed that SnO2 thin films having a smooth surface morphology. The optical properties in the visible range showed that the deposited layers have a high transmission factor. The optical band gap energy varies in the range of 3.61–3.73 eV. Finally, ultraviolet (UV) detection properties of samples as an active layer in UV photodetector devices were investigated. Current-voltage characteristics of the SnO2 thin films are performed under dark and light environment, which show low dark current of 22.9 nA with a linear behavior and high current ration > 104 under 2 V applied voltage and 120 min as annealing time. Whereas, high photocurrent is observed for samples annealing for 30 min. Moreover, the transient photoresponse of the fabricated device is reported under different annealing times.

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International audience; Single crystal Silicon (Si) layers have been deposited by molecular beam epitaxy on double-layer porous silicon (PSi). We show that a top thin layer with a low porosity is used as a seed layer for epitaxial growth. While, the underlying higher porosity layer is used as an easily detectable etch stop layer. The morphology and structure of epitaxial Si layer grown on the double-layer PSi are investigated by high resolution X-ray diffraction and transmission electron microscopy. The results show that, an epitaxial Si layer with a low defect density can be grown. Epitaxial growth of thin crystalline layers on double-layer PSi can provide opportunities for silicon-on-insulator applications and Si-based solar cells provided that the epitaxial layer has a sufficient crystallographic quality.

La region des Aures reste l’une des zones les plus exposees au phenomene de l’erosion hydrique en Algerie, du fait de la forte agressivite climatique, du relief accidente, de la predominance des terrains sensibles et d’une couverture vegetale qui ne joue pas son role protecteur. Dans un souci de servir a la protection du milieu agricole et de l’infrastructure hydraulique a l’aval, avec notamment le barrage de Koudiat El Medouar, la presente etude a pour objectif principal la modelisation cartographique de l’alea erosion au niveau du bassin versant de l’oued Chemoura, bassin representatif des Aures. Le modele fait appel a un systeme d’information geographique (SIG); il integre quatre facteurs controlant l’erosion : la friabilite des materiaux, la declivite, l’erosivite des pluies et l’occupation des sols. Le resultat est une carte synthetique de l’alea erosion des sols qui localise les zones les plus menacees et prioritaires pour d’eventuelles interventions d’amenagement. Une etude statistique sur la relation debit solide-debit liquide a ete elaboree. Pour cela, des mesures effectuees sur la periode 1969-1994 au niveau de la station de Chemoura ont ete exploitees. Les resultats ont permis de mettre en evidence une degradation specifique importante variant entre 50 et 1 360 t/km 2 et par an.

International audience; Thick porous silicon (PS) buffer layers are used as sacrificial layers to epitaxially grow planar and fully relaxed Ge membranes. The single crystal Ge layers have been deposited by molecular beam epitaxy (MBE) on PS substrate. During deposition, the pore network of PS layers has been filled with Ge. We investigate the structure and morphology of PS as fabricated and after annealing at various temperatures. We show that the PS crystalline lattice is distorted and expanded in the direction perpendicular to the substrate plane due to the presence of chemisorbed –OH. An annealing at high temperature (> 500 °C), greatly changes the PS morphology and structure. This change is marked by an increase of the pore diameter while the lattice parameter becomes tensily strained in the plane (compressed in the direction perpendicular). The morphology and structure of Ge layers are investigated by transmission electron microscopy, high resolution X-ray diffraction and atomic force microscopy as a function of the deposition temperature and deposited thickness. The results show that the surface roughness, level of relaxation and Si-Ge intermixing (Ge content) depend on the growth temperature and deposited thickness. Two sub-layers are distinguished: the layer incorporated inside the PS pores (high level of intermixing) and the layer on top of the PS surface (low level of intermixing). When deposited at temperature > 500 °C, the Ge layers are fully relaxed with a top Si1 − xGex layer x = 0.74 and a very flat surface. Such layer can serve as fully relaxed ultra-thin SiGe pseudo-substrate with high Ge content. The epitaxy of Ge on sacrificial soft PS pseudo-substrate in the experimental conditions described here provides an easy way to fabricate fully relaxed SiGe pseudo-substrates. Moreover, Ge thin films epitaxially deposited by MBE on PS could be used as relaxed pseudo-substrate in conventional microelectronic technology.

International audience; Porous silicon (PSi) layers are used as templates to grow epitaxial planar and fully relaxed Ge pseudo-substrates. An annealing at 600 °C, dramatically changes the PSi morphology and produces compliant template layers which serve in a second step, as substrate for the epitaxy of fully relaxed SiGe layers with a Ge content between 50% and 94%. The SiGe pseudo-substrates produced by such process exhibit a remarkable planar surface resulting from the penetration of Ge inside the pores. They could be integrated into conventional microelectronic technology for the subsequent deposition of active layers such as tensily strained Si or relaxed Ge.

International audience; In this work, a new multigate pH-ISFET sensor design, called the Junctionless Gate All Around (GAA) ISFET sensor (JGAAISFET), and its numerical analysis have been proposed, investigated and expected to improve the fabrication process and the sensitivity behavior for pH-ISFET sensor-based applications. The numerical analysis has been used to predict and to compare the performances of the proposed design and conventional pH-ISFET, where the comparison of device architectures shows that the proposed pH-JISFET sensor exhibits a superior performance with respect to the conventional pH-ISFET in term of fabrication process and electrical performances. The numerical model provides a basic framework to account for the electronic and chemical performances in future multigate pH-ISFET designs, being easily adaptable to gate structures as the double-gate (DG) or tri-gate (TG). Moreover, the proposed design has linear pH sensitivities of approximately 59.6 mV/pH for wide concentration range (from pH = 2 to pH = 12). The obtained results make the Junctionless ISFET sensor a promising candidate for future integrated CMOS-based sensors.