257 results on '"Demuynck, S."'
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2. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
3. 1426 Deletion of hoxc13 in frogs reveals key steps in the molecular evolution of cornified skin appendages
4. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
5. Low-Voltage Scaled 6T FinFET SRAM Cells
6. Standardized 4-point scoring scale of [18F]-FDG PET/CT imaging helps in the diagnosis of renal and hepatic cyst infections in patients with autosomal dominant polycystic kidney disease: A validation cohort
7. Comparison of the interest of four types of organic mulches to reclaim degraded areas (Part 2): Microbial activities and abiotic factors
8. Reliability of Barrierless PVD Mo
9. A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier
10. Failure mechanisms of PVD Ta and ALD TaN barrier layers for Cu contact applications
11. An investigation of ultra low- k dielectrics with high thermal stability for integration in memory devices
12. Integrating ENSEMBLE™ PMD low- k at the PMD level of CMOS logic circuits
13. Electric-field gradients used to measure atomic short range order: as a case-study
14. Buried Power Rail Scaling and Metal Assessment for the 3 nm Node and Beyond
15. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
16. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
17. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
18. Virtual Process-Based Spacer & Junction Optimization for an Inverter Circuit
19. Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects
20. Isolation and structural characterization of hepatic metallothionein from the roach (shape Rutilus rutilus L.)
21. Effects of Organophosphate and Carbamate Pesticides on Acetylcholinesterase and Choline Acetyltransferase Activities of the Polychaete Nereis diversicolor
22. The reliability margin of interconnects for advanced memory technologies
23. Correlation between barrier integrity and TDDB performance of copper porous low-k interconnects
24. Buried power rail integration for CMOS scaling beyond the 3 nm node
25. Ge oxide scavenging and gate stack nitridation for strained Si0.7Ge0.3 pFinFETs enabling 35% higher mobility than Si
26. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
27. High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG
28. Does adding fly ash to metal-contaminated soils play a role in soil functionality regarding metal availability, litter quality, microbial activity and the community structure of Diptera larvae?
29. Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local Interconnects
30. Isopod physiological and behavioral responses to drier conditions: An experiment with four species in the context of global warming
31. Isolation and structural characterization of hepatic metallothionein from the roach ( Rutilus rutilus L)
32. Analysis of junctions formed in strained Si/SiGe substrates
33. Spin fluctuations in Y 1− xSc xMn 2 and Y(Mn 1− xAl x) 2 observed by perturbed-angular-correlation spectroscopy
34. Longitudinal spin-density-wave ordering in thin epitaxial chromium layers
35. Patterning spacer source drain cavities in CFET devices
36. Oscillation of the Fe and Co magnetic moments at the sharp (1-10) Fe/Co interface and temperature dependence of the near interface moments
37. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
38. Enabling CMOS Scaling Towards 3nm and Beyond
39. Replacement Metal Contact Using Sacrificial ILD0 for Wrap Around Contact in Scaled FinFET Technology
40. The Complementary FET (CFET) for CMOS scaling beyond N3
41. Self-Aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24 nm Pitch and Beyond.
42. Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration
43. CMOS Integration of Thermally Stable Diffusion and Gate Replacement (D&GR) High-k/Metal Gate Stacks in DRAM Periphery Transistors
44. Ultralow resistive wrap around contact to scaled FinFET devices by using ALD-Ti contact metal
45. Overgewicht, obesitas en kanker
46. Improvement of the CMOS characteristics of bulk Si FinFETs by high temperature ion implantation
47. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
48. Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?
49. Towards high performance sub-10nm finW bulk FinFET technology
50. Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass
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