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This paper presents a fully on-chip HV-regulated DC–DC boost converter for the power management unit of an electrical neural stimulator. The core of the DC–DC converter consists of a 4x4 array of individually-configurable charge pumps. The rows and columns of the array can be dynamically enabled or disabled, thus extending the range of suitable output voltages and load currents. Additionally, the converter includes a feedback loop for output voltage regulation which allows responding to abrupt changes in the load current within a few microseconds. The circuit has been designed in a standard 180 nm 1.8V/3.3V CMOS process and occupies an active area of 2.1 mm2. An exhaustive experimental characterization of the proposed circuit was carried out. Experimental results demonstrate that, for an input voltage of 3 V, the DC–DC converter's regulated output ranges from 4.2 V to 13.2 V under load currents of 0.1–4 mA. Maximum delivered power is around 48 mW. The power efficiency of the converter at the highest achievable output voltage under a 4 mA load current is higher than 65% for input voltages above 2.4 V.

This paper presents a fully on-chip HV-regulated DC–DC boost converter for the power management unit of an electrical neural stimulator. The core of the DC–DC converter consists of a 4x4 array of individually-configurable charge pumps. The rows and columns of the array can be dynamically enabled or disabled, thus extending the range of suitable output voltages and load currents. Additionally, the converter includes a feedback loop for output voltage regulation which allows responding to abrupt changes in the load current within a few microseconds. The circuit has been designed in a standard 180 nm 1.8V/3.3V CMOS process and occupies an active area of 2.1 mm2. An exhaustive experimental characterization of the proposed circuit was carried out. Experimental results demonstrate that, for an input voltage of 3 V, the DC–DC converter’s regulated output ranges from 4.2 V to 13.2 V under load currents of 0.1–4 mA. Maximum delivered power is around 48 mW. The power efficiency of the converter at the highest achievable output voltage under a 4 mA load current is higher than 65% for input voltages above 2.4 V.

This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA.

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 mm2. Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.

This paper describes a neural stimulator with 4 × V DD compliance voltage, delivering up to 2.08 mA, and implemented in the TSMC 180 nm 1.8V/3.3V CMOS Process. The wide range of stimulation currents and high compliance voltage makes it suitable for stimulation applications both in rodents and mammals. Besides, it can be configured both as electrical and optical stimulator. Stacked transistor cells with dynamic gate biasing have been used for withstanding voltages well above the nominal supply. An on-chip programmable high-voltage generator supplied the stimulator front-end. The system has been fabricated, occupying an active area of 2.34 mm 2 . The circuit has been experimentally tested by connecting it to a custom µelectrode array which was immersed into a phosphate-buffered saline solution.

This paper proposes a high-voltage floating level shifter with a periodically-refreshed charge pump topology. Designed and fabricated in a standard 1.8 V/3.3 V CMOS process, the circuit can withstand shifting voltages from 3 V to 8.5 V with a delay response of 1.8 ns and occupies 0.008 mm2. The proposed circuit has been used in a multi-stage charge pump for programming its voltage conversion ratio. Experimental results show that the level shifters successfully enable/disable the stages of the charge pump, thus modifying its output voltage between 5.35 V and 12.4 V for an output current of 3 mA.

This paper proposes a system to transfer both mW-power and Mbps-data over an inductive link using a single pair of coils. The system is able to handle a wide range of loads by implementing a load adapter block that divides the operation into two phases: a Power Transfer Phase (PTP) and a Data Transfer Phase (DTP). On the one hand, during PTP, a constant amount of power is drawn from the inductive link, regardless of the current demanded by the load. On the other hand, during DTP, the load is powered with external capacitors, allowing the inductive link to be used for data transmission. With this architecture, intended to be used in a neural implant, power can be delivered to a wide range of loads without affecting the uplink/downlink data communication reliability and with no need of extra coils. Thus, the proposed solution permits minimizing the overall size of the neural implant. An electrical mixed-signal model of the system is described and implemented in MATLAB Simulink through Simscape Electrical and Stateflow toolboxes. Simulations performed on the electrical model of the system are shown and discussed.

This paper presents a fully integrated high-voltage (HV) neural stimulator with on-chip HV generation. It consists of a neural stimulator front-end that delivers stimulation currents up to 2.08 mA with 5 bits resolution and a switched-capacitor DC-DC converter that generates a programmable voltage supply from 4.2 V to 13.2 V with 4 bits resolution. The solution was designed and fabricated in a standard 180 nm 1.8 V/3.3 V CMOS process and occupied an active area of 2.34 m m 2 . Circuit-level and block-level techniques, such as a proposed high-compliance voltage cell, have been used for implementing HV circuits in a low-voltage CMOS process. Experimental validation with an electrical model of the electrode–tissue interface showed that (1) the neural stimulator can handle voltage supplies up to 4 times higher than the technology’s nominal supply, (2) residual charge—without passive discharging phase—was below 0.12% for the whole range of stimulation currents, (3) a stimulation current of 2 mA can be delivered with a voltage drop of 0.9 V, and (4) an overall power efficiency of 48% was obtained at maximum stimulation current.