The market for Wi-Fi receiver designs for latest Wi-Fi standards, that cover RF bands in the 2.4 GHz, 5 GHz and 6 GHz spectrum, require increasingly stringent power consumption limitations as more of the market is driven towards battery-powered devices. In order to meet those needs, it is crucial to explore different ways of reducing power consumption in various receiver blocks. One such power consumer can be the LO generating stage. As present standards require higher operating frequencies, circuit blocks such as frequency synthesizers, filters and amplifiers lead to increased power requirements in the receiver chain. In addition, issues such as spurious tones from inductive coupling, as well as IM2 and IM3 mixing products, may necessitate additional filtering stages, leading to stricter requirements for the remainder of the circuit. This thesis explores the possibility of reducing power consumption in the LO generation stage by implementing analog calibration schemes for a frequency synthesizer block, which would enable running the LO source at a lower frequency. The LO is then brought to the required frequency through the use of the Edge-Combining Delay-Locked Loop (EC DLL) based synthesizer. This would relax energy requirements in the LO stage, which can then be better used in the rest of the receiver chain. Two self-calibration systems are proposed for the synthesizer. A mathematical support is derived and explained, formulating expressions which help quantifying the expected synthesizer performance, denoted as Spur-to-Carrier Ratio (SCR). A design flow for optimal spurious performance in EC DLL is suggested. Then, a design for the calibration mechanisms is constructed and simulated in 22 nm CMOS technology. Specifications for the required performance are derived based on the IEEE802.11ax standard interferer scenarios and final results are discussed. The circuit is only realised as a proof-of-concept schematic de 800 mV. The final circuit improves the SCR perfo, The technology in today's world is in a continuous evolution. The push is always towards solutions that are more inter-connected, consume less battery power and provide better services to meet users' needs. Moreover, future devices will need to gather and communicate even more data between themselves to better identify what is demanded of them and what is the best solution for this. For example, if at the end of every working day you prefer to take a long bath, then your phone should be able to gather all of this information, identify your needs and communicate them to the smart devices in your bathroom to have it prepared by the time you arrive home. An easy and already available solution to provide all of this communication quick and efficient could be to use Wi-Fi to integrate future smart devices. Wi-Fi networks are already available all around us in our everyday life, especially in everyone's homes. However, with increasing worry for sustainable technology and ever increasing energy demands, the devices of next generation should use as little energy as possible for their communications. This thesis aims to provide one possible solution for more battery-efficient wireless communication, in the form of a hardware component. When two devices communicate, each of them uses a physical transmitter to send data, a physical receiver to intercept it and an antenna, which actually converts the information of interest to signal waves in the radio frequency (RF) spectrum. These RF signals travel through the air, over long distances, to transfer information between two devices. The good thing is that all of the infrastructure for these Wi-Fi telecommunications is already there. So how can they be made more energy efficient? Well, a big part of Wi-Fi communications is represented by time spent waiting and receiving information. So, if the receiver can be constructed in a way that consumes less power, while maintaining the same performance, then a lot of battery life could be