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1,668 results on '"Delay-locked loop"'

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1. 用于新型符号的频偏补偿和解调的算法与电路.

2. General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme.

3. Design of a Clock Doubler Based on Delay-Locked Loop in a 55 nm RF CMOS Process.

4. A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency Ranges.

5. A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction.

6. Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques.

7. A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection.

8. A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL.

9. Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line.

10. Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit.

11. 28nm FDSOI Ultra Low Power 1.5–2.0 GHz Factorial-DLL Frequency Synthesizer.

12. A small area DLL-based clock generator using duty cycle controllable cyclic VCDL.

13. A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.

14. An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications.

15. A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS.

16. A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL.

18. Investigation of Analog Calibration Systems for Spurious Tone Suppression in Frequency Triplers

19. A wide-range all-digital phase inversion DLL for high-speed DRAMs.

20. A hybrid time-to-digital converter based on sliding scale technique suitable for random time-of-flight measurement.

21. A Reconfigurable DLL-Based Digital-to-Time Converter Using Charge Pump Current Interpolation and Digital Predistortion Linearization.

23. A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

24. Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop

26. Low‐power and wide‐band delay‐locked loop with switching delay line.

27. An anti-boundary switching fine-resolution digital delay-locked loop.

28. High Throughput Low Complexity and Low Power ePiBM RS Decoder Using Fractional Folding

29. Delay Tracking of Spread-Spectrum Signals for Indoor Optical Ranging

30. Low-power high-speed phase frequency detector based on carbon nano-tube field effect transistors

31. Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor

33. Analysis of impact of group delay on slope distortion of S-curve in delay locked loop

36. Design of multi standard near field communication outphasing transmitter with modulation wave shaping

37. Low‐jitter DLL applied for two‐segment TDC.

38. A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops.

39. 脉冲超宽带测控信号时延的精密跟踪方法.

40. A study of phase noise suppression in reference multiple digital PLL without DLLs

41. Design and simulation of a new wireless power transfer circuit with a single-stage regulating rectifier for flexible sensor patches

42. GNSS Receiver Signal Tracking

43. An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits

44. An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications

45. Measurement and Analysis of System-Level ESD-Induced Jitter in a Delay-Locked Loop

46. Multipath Estimating Delay Lock Loop for LTE Signal TOA Estimation in Indoor and Urban Environments

48. Unequal‐weighted TCAR algorithm for long‐baseline static triple‐frequency ambiguity resolution

49. Enhancing Nutt-Based Time-to-Digital Converter Performance With Internal Systematic Averaging

50. A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS

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