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This paper is the first to present an implementation of a cryptographic circuit in 28nm FD-SOI using near-threshold design. The implemented cipher, Ketje Jr, is a lightweight authenticated encryption algorithm. The energy consumption of representative authenticated encryption operations as well as the information leakage through the power consumption side-channel are evaluated. The results show that an ultra-low energy implementation can be achieved, and that the near-threshold design has little influence on the Signal to Noise Ratio in the power measurements of our chip. ispartof: pages:258-262 ispartof: Proceedings of the 19th ACM International Conference on Computing Frontiers pages:258-262 ispartof: Computing Frontiers location:Turin, Italy date:17 May - 19 May 2022 status: published

© 2018, Blackwell Publishing Ltd. All rights reserved. We present a 350°C self-aligned dual-gate a-IGZO backplane technology with a monolithically integrated multi-layer high-temperature thin-film barrier for flexible AMOLED. Thin-film barrier properties and TFT technology are optimized on 320 x 352mm substrates, and demonstrated in a flexible QQVGA 100 ppi AMOLED display prototype. ispartof: pages:1577-1580 ispartof: Digest of Technical Papers - SID International Symposium vol:49 issue:1 pages:1577-1580 status: published

ispartof: pages:494-497 ispartof: Society for Information Display International Symposium Digest of Technical Papers pages:494-497 ispartof: SID international Symposium location:Los Angeles, CA, USA status: Published online

© (2017) by SID-the Society for Information Display. All rights reserved. We present a qHD (960×540 with 3 sub-pixels) top-emitting ‘AMOLED display with 340ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimidefoil with humidity barrier. The back plane process flow is based on a 7 layer photolithography process with a CD=4um. We implement a 2TIC pixel engine and use commercial source driver IC made for LTPS. By using IGZO TFT and leveraging the extremely low off-current, we can switch-offthe power to the source and gate driver while maintaining the image un-changed for several minutes We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared to normal (continuous) operation. We show that with further increase in resolution, the power saving through state retention will be even more significant. ispartof: Journal of the Society for Information Display vol:25 issue:4 pages:222-228 status: published

Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique's strong potential for via layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition. © 2016 Society of Photo-Optical Instrumentation Engineers (SPIE).

In this work, an FFT architecture supporting variable FFT sizes, 128~2048/1536, is proposed. This implementation is a combination of a 2p point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput by exploiting single tone pruning with low control logic overhead. The proposed FFT processor is implemented on a Xilinx Virtex 5 FPGA. It occupies only 3148 LUTs and 612 kb memory in FGPA and calculates 1536 point FFT less than 3092 clock cycles with output pruned settings. ispartof: pages:266-270 ispartof: Signal Processing Conference (EUSIPCO), 2014 Proceedings of the 22nd European pages:266-270 ispartof: European Signal Processing Conference (EUSIPCO) location:Lisbon, Portugal date:1 Sep - 5 Sep 2014 status: published

We present an 8b general-purpose microprocessor realized in a hybrid oxide-organic complementary thin-film technology. The n-type transistors are based on a solution-processed n-type metal-oxide semiconductor, and the p-type transistors use an organic semiconductor. As compared to previous work utilizing unipolar logic gates [1], the higher mobility n-type semiconductor and the use of complementary logic allow for a >50x speed improvement. It also adds robustness to the design, which allowed for a more complex and complete standard cell library. The microprocessor consists of two parts, a processor core chip and an instruction generator. The instructions are stored in a Write-Once-Read-Many (WORM) memory formatted by a post-fabrication inkjet printing step, called Print-Programmable Read-Only Memory (P2ROM). The entire processing was performed at temperatures compatible with plastic foil substrates, i.e., at or below 250°C [2]. © 2014 IEEE.

A 60 GHz receiver front-end with 6 GHz RF bandwidth and 4 GHz baseband bandwidth is presented. The chip consists of an LNA and quadrature direct downconversion mixers, directly connected to a high impedant digital baseband. An on-chip poly-phase filter is used to generate the necessary quadrature LO signals from an external reference. A fully differential architecture is used to alleviate the influences of parasitics and avoid common-mode stability problems. A test chip was fabricated in a 1P10M 40nm CMOS process. A noise figure of 10.8 dB and input P1dB of -9dBm were measured. The front-end has a power consumption of 80mWfrom a 1.1V supply. © 2013 EuMA. ispartof: pages:9-12 ispartof: Proceedings of the 8th European Microwave Integrated Circuits Conference pages:9-12 ispartof: European Microwave Integrated Circuits Conference (EuMIC) location:Nuremberg date:7 Jan - 9 Jan 2013 status: published

ispartof: pages:1-12 ispartof: Proc. SEFI Annual Conference 2013 pages:1-12 ispartof: European Society for Engineering Education Annual Conference 2013 location:Leuven, Belgium date:16 Sep - 20 Sep 2013 status: published

In this chapter, fully integrated organic RFID tags are demonstrated. These tags are inductively-coupled at a base frequency of 13.56 MHz and can be read out at distances up to 10 cm, which is the expected readout distance for proximity readers. We also demonstrate next generation transponder chips, fabricated in a dual-gate technology. The additional gate, backgate, is used to control the threshold voltage and allows integration into more robust unipolar, dual-VT transponder chips. Finally, we realized an 8-bit transponder chip having data rates that are EPC-compatible. This has been achieved in our thin-film transistor technology by introducing a high-k Al2O 3 gate dielectric, by scaling the channel lengths down to 2 mm and by reducing the overlap capacitance of the parasitic source-gate and drain-gate capacitors. © 2011 Springer Science+Business Media B.V.

The complex analog correlating (CAC) receiver is an excellent candidate for low power, low data rate pulsed UWB communication, but only in ideal AWGN channels. This paper adapts the traditional architecture and acquisition scheme of this receiver for operation in realistic multipath channels. Two schemes are presented: a high performance scheme, and a simpler, but easy to implement and low power scheme. Monte-Carlo simulations illustrate the performance improvement in realistic 802.15.4a (LOS and NLOS) channels. The receiver's power consumption can be traded for performance by tuning the number of resolved path components. The system outperforms the traditional CAC receiver and the transmitted reference receiver in all environments.