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405 results on '"Decoutere, Stefaan"'

1. Vertical GaN Devices: Process and Reliability

Author

You, Shuzhen, Geens, Karen, Borga, Matteo, Liang, Hu, Hahn, Herwig, Fahle, Dirk, Heuken, Michael, Mukherjee, Kalparupa, De Santi, Carlo, Meneghini, Matteo, Zanoni, Enrico, Berg, Martin, Ramvall, Peter, Kumar, Ashutosh, Björk, Mikael T., Ohlsson, B. Jonas, and Decoutere, Stefaan

Subjects
Physics - Applied Physics
Abstract

This paper reviews recent progress and key challenges in process and reliability for high-performance vertical GaN transistors and diodes, focusing on the 200 mm CMOS-compatible technology. We particularly demonstrated the potential of using 200 mm diameter CTE matched substrates for vertical power transistors, and gate module optimizations for device robustness. An alternative technology path based on coalescence epitaxy of GaN-on-Silicon is also introduced, which could enable thick drift layers of very low dislocation density., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][ECSEL Joint Undertaking (JU)][UltimateGaN][grant agreement No 826392]

Published
2021
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8. Enhancing the Forward Gate Bias Robustness in p‐GaN Gate High‐Electron‐Mobility Transistors through Doping Profile Engineering.

Author

Borga, Matteo, Posthuma, Niels, Vohra, Anurag, Bakeroot, Benoit, and Decoutere, Stefaan

Subjects
BREAKDOWN voltage, STRAY currents, RELIABILITY in engineering, THERMAL engineering, TRANSISTORS, MODULATION-doped field-effect transistors
Abstract

This article presents a study on the improvement of the gate robustness and reliability of p‐GaN gate high‐electron‐mobility transistors (HEMTs) by doping profile engineering and by performing a thermal treatment. The reduction of the p‐doping concentration at the Schottky interface using a graded magnesium (Mg) profile in the p‐GaN layer and introducing a top Si‐GaN cap layer is proposed, combined with a high‐temperature anneal step after the gate patterning. The results show that the proposed approach enhances the gate breakdown voltage, reduces the gate leakage current, and increases the time to failure under constant voltage stress, while ensuring stable dynamic behavior and off‐state leakage performance under high‐voltage stress. [ABSTRACT FROM AUTHOR]

Published
2024
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9. Extending Electrostatic Modeling for Schottky p-GaN Gate HEMTs: Uniform and Engineered p-GaN Doping

Author

Alaei, Mojtaba, Borga, Matteo, Fabris, Elena, Decoutere, Stefaan, Lauwaert, Johan, and Bakeroot, Benoit

Abstract

This article presents a comprehensive analytical framework for modeling p-GaN gate high-electronmobility transistors (HEMTs) based on rigorous solution of the Poisson and Schrödinger equations. It focuses primarily on the calculation of the 2-D electron gas (2DEG), voltage variation across the junction ( $\Delta V_j$ ), and AIGaN barrier ( $\Delta V_b$ ) for the entire range of forward gate bias until gate breakdown. Our model considers the impact of AIGaN barrier height saturation. In addition, we demonstrate our model with the engineered p-GaN doping profile that yields higher forward gate breakdown voltages. Gate capacitance and breakdown voltage have been modeled for both uniform and engineered p-GaN doping profiles. The viability and accuracy of the proposed model are demonstrated through comparisons with empirical measurement data and TCAD simulations.

Published
2024
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11. Time-dependent conduction mechanisms in reversed stepped superlattice layers of GaN HEMTs on 200 mm engineered substrates.

Author

Chen, Zequan, Uren, Michael J., Huang, Peng, Sanyal, Indraneel, Smith, Matthew D., Vohra, Anurag, Kumar, Sujit, Decoutere, Stefaan, Bakeroot, Benoit, and Kuball, Martin

Subjects
SUBSTRATES (Materials science), GALLIUM nitride, LEAKAGE
Abstract

Time-dependent conduction in epitaxial superlattice (SL) strain relief layers of GaN high electron mobility transistors on 200 mm engineered substrates with a poly-AlN core was observed and analyzed. This phenomenon occurs when the devices were operated with substrate bias of ∼−300 V for 101–103 s. The formation of the conduction path is related to trap-assisted leakage through the SLs on the engineered substrates; de-trapped carriers spread out vertically and laterally within a portion of the SLs, leading to a higher electrical field across the rest of the layers. This conduction mechanism may be hidden during the devices' normal operation (target 650–1200 V). It could lead to undesired effects during the operation of the devices, such as a time-dependent dynamic Ron. More resistive SLs will potentially reduce the impact of this phenomenon. [ABSTRACT FROM AUTHOR]

Published
2024
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13. Modeling Gate Leakage Current for p-GaN Gate HEMTs With Engineered Doping Profile

Author

Alaei, Mojtaba, Borga, Matteo, Fabris, Elena, Decoutere, Stefaan, Lauwaert, Johan, and Bakeroot, Benoit

Abstract

The forward bias gate leakage current and forward gate breakdown voltage are important properties of p-GaN gate high-electron-mobility transistors (HEMTs). An engineered doping profile in the p-GaN layer results in a higher gate breakdown voltage and a lower forward bias gate leakage current. The use of such a technique puts additional requirements on the compact models that are used for these p-GaN gate HEMTs. An accurate compact model is needed, which considers a change in the doping profile in the p-GaN layer of these devices. This article reviews the relationship between the gate bias and the voltage drops at the different junctions in the gate structure (i.e., at the metal/p-GaN Schottky junction and the p-GaN/AIGaN/GaN junctions) considering an engineered doping profile. This relationship is then used to model the drain-source current ( $I_{\mathrm {DS}}$ ) and gate leakage current ( $I_G$ ). Three different regimes in the gate current have been considered in the model: Poole-Frenkel (PF) under low bias, thermionic emission (TE) in the medium bias range, and thermally assisted tunneling (TAT) at higher bias.

Published
2024
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14. Toward Understanding the Failure Mechanism in p-GaN Gate HEMTs Operating in Reverse Conduction Diode Mode

Author

Lin, Wei-Syuan, Bakeroot, Benoit, Huang, Zhen-Hong, Lo, Ting-Chun, Borga, Matteo, Wellekens, Dirk, Posthuma, Niels, Decoutere, Stefaan, and Wu, Tian-Li

Abstract

In this study, we investigate the reverse conduction diode mode failure mechanism in p-GaN gate high electron mobility transistors (HEMTs) using TCAD simulations and emission microscopy (EMMI). First, we observe a significant increase in gate leakage current when ${V}_{\text {DS}}$ is swept to −15 V while ${V}_{\text {GS}} =0$ V, indicating gate breakdown occurring with sufficient negative bias. Second, TCAD simulations are conducted to gain further insight into the failure locations and mechanisms. The simulations reveal high electric fields in the Schottky junction close to the interface between the metal and the p-GaN. This finding suggests that the gate region is likely the location leading to increased gate current and breakdown during the reverse conducting operation of the p-GaN gate HEMT. Lastly, EMMI measurements are performed on a device exhibiting high gate leakage current during reverse conduction diode mode operation. The EMMI results show bright spots in the gate region, which align with the failure location identified by the TCAD simulations. These results emphasize the importance of optimizing the Schottky/p-GaN junction to enhance the robustness of the p-GaN gate HEMT under reverse conduction diode mode operation.

Published
2024
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32. Vertical GaN devices: Process and reliability

Author

You, Shuzhen, primary, Geens, Karen, additional, Borga, Matteo, additional, Liang, Hu, additional, Hahn, Herwig, additional, Fahle, Dirk, additional, Heuken, Michael, additional, Mukherjee, Kalparupa, additional, De Santi, Carlo, additional, Meneghini, Matteo, additional, Zanoni, Enrico, additional, Berg, Martin, additional, Ramvall, Peter, additional, Kumar, Ashutosh, additional, Björk, Mikael T., additional, Ohlsson, B. Jonas, additional, and Decoutere, Stefaan, additional

Published
2021
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38. Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Author

Mukherjee, Kalparupa, primary, De Santi, Carlo, additional, Borga, Matteo, additional, Geens, Karen, additional, You, Shuzhen, additional, Bakeroot, Benoit, additional, Decoutere, Stefaan, additional, Diehle, Patrick, additional, Hübner, Susanne, additional, Altmann, Frank, additional, Buffolo, Matteo, additional, Meneghesso, Gaudenzio, additional, Zanoni, Enrico, additional, and Meneghini, Matteo, additional

Published
2021
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39. Understanding the Leakage Mechanisms and Breakdown Limits of Vertical GaN-on-Si p+n−n Diodes: The Road to Reliable Vertical MOSFETs

Author

Mukherjee, Kalparupa, primary, De Santi, Carlo, additional, Buffolo, Matteo, additional, Borga, Matteo, additional, You, Shuzhen, additional, Geens, Karen, additional, Bakeroot, Benoit, additional, Decoutere, Stefaan, additional, Gerosa, Andrea, additional, Meneghesso, Gaudenzio, additional, Zanoni, Enrico, additional, and Meneghini, Matteo, additional

Published
2021
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40. High-frequency noise performance of 60-nm gate-length FinFETs

Author

Raskin, Jean-Pierre, Pailloncy, Guillaume, Lederer, Dimitri, Danneville, Francois, Dambrine, Gilles, Decoutere, Stefaan, Mercha, Abdelkarim, and Parvais, Bertrand

Subjects
Electromagnetic noise -- Evaluation, Field-effect transistors -- Evaluation, Gates (Electronics) -- Analysis, Business, Electronics, Electronics and electrical industries
Abstract

The radio-frequency noise performance of FinFETs from a 60-nm gate length is investigated. It is observed that the fringing capacitance of the 3-D and multifin structure of the FinFETS is responsible for the degradation of its noise performance.

Published
2008

41. SiGe HBTs with normal high-speed emitter-up and reverse low-power collector-up operation

Author

Li Jen Choi, Sibaja-Hernandez, Arturo, Venegas, Rafael, Van Huylenbroeck, Stefaan, and Decoutere, Stefaan

Subjects
Bipolar integrated circuits -- Design and construction, Bipolar integrated circuits -- Comparative analysis, Bipolar transistors -- Design and construction, Bipolar transistors -- Comparative analysis, Silicon compounds -- Mechanical properties, Business, Electronics, Electronics and electrical industries
Abstract

Studies have shown that SiGe heterojunction bipolar transistors (HBTs), which are optimized for high-speed performance in the forward mode of operation, have displayed an excellent performance in the reverse mode of operation. The simultaneous availability of a high-speed performance in the forward mode and a low-power performance in the reverse mode has offered additional flexibility to optimize circuit performance in terms of speed, area and power.

Published
2008

42. The potential of FinFETs for analog and RF circuit applications

Author

Wambacq, Pier, Verbruggen, Bob, Scheir, Karen, Borremans, Jonathan, Dehan, Morin, Linten, Dimitri, De Heyn, Vincent, Van der Plas, Geert, Mercha, Abdelkarim, Parvais, Bertrand, Gustin, Cedric, Subramanian, Vaidy, Collaert, Nadine, Jurczak, Malgorzata, and Decoutere, Stefaan

Subjects
Complementary metal oxide semiconductors -- Properties, Field-effect transistors -- Design and construction, Analog integrated circuits -- Research, Nanotechnology -- Research, Business, Computers and office automation industries, Electronics, Electronics and electrical industries
Abstract

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and Si[O.sub.2] with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeterwave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz. Index Terms--Electrostatic discharges (ESDs), fin-shaped fieldeffect transistor (FinFET), mixed analog integrated circuits, nanotechnology.

Published
2007

43. Planar bulk MOSFETs versus FinFETs: An analog/RF perspective

Author

Subramanian, Vaidy, Paravais, Bertrand, Borremans, Jonathan, Mercha, Abdelkarim, Linten, Dimitri, Wambacq. Piet, Loo, Josine, Dehan, Morin, Gustin, Cedric, Collaert, Nadine, Kubicek, Stefan, Lander, Robert, Hooker, Jacob, Cubaynes, Florence, Donnay, Stephane, Jurezak, Malgorzata, Groeseneken, Guido, Sasen, Willy, and Decoutere, Stefaan

Subjects
Metal oxide semiconductor field effect transistors -- Design and construction, Circuit design -- Analysis, Electric circuit analysis, Circuit designer, Integrated circuit design, Business, Electronics, Electronics and electrical industries
Abstract

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveal an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the key advantages over bulk MOSFETs including reduced leakage, excellent subthreshold slope, and a better voltage gain without degradation of noise or linearity.

Published
2006

48. Reliability of p-GaN Gate HEMTs in Reverse Conduction

Author

Cingu, Deepthi, primary, Li, Xiangdong, additional, Bakeroot, Benoit, additional, Amirifar, Nooshin, additional, Geens, Karen, additional, Jacobs, Kristof J. P., additional, Zhao, Ming, additional, You, Shuzhen, additional, Groeseneken, Guido, additional, and Decoutere, Stefaan, additional

Published
2021
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