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A novel design and measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52µW at a bitclock of 50-kHz and of 0.85µW at 100-kHz with a 1.2-V supply. The Figure-of-Merit reached with such implementation is of 66 fJ/conversion-step. The ADC was realised in the NXP CMOS 0.14µm technology with an area of 0.35 mm2. Only four metal layers were used in order to allow 3D integration of the sensors.

The design and first measuring results of an ultra-low power 12 bit successive-approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for low power consumption. The power consumption is [email protected] from a 1.2V supply with a sample clock of 3.125kHz and [email protected] at 6.25kHz. This gives 136pJ per conversion or 66fJ per conversion step. As per authors' knowledge, 66fJ per conversion step is the best reported so far. The ADC was realised in the NXP CMOS [email protected] technology; the area was 0.35mm^2. Only four metal layers were used in order to allow 3D integration of the sensors.

Design strategies for power effective and high resolution Successive-Approximation ADCs for autonomous multi-sensor systems are discussed. Specifically, an optimisation for lowest possible power consumption of comparators is addressed and evaluated using both simulations and measurements of a fabricated Si test-chip. The proposed design solution is capable to provide a 12-bit resolution at 50-kHz with only 0.1uW power consumption on a 1.2-V supply. The achieved Figure-of-Merit is 165 ƒJ/convertion-step is, to our knowledge, the best ever reported. The complete ADC area is 0.35 mm2 in NXP 0.14um CMOS technology with only three metal layers.

The resistive-switching phase-change memory (PCM) is gaining increasing interest as a potential flash replacement, mainly due to scalability, faster writing and better endurance. PCM cells are typically programmed to the high- resistive amorphous state using a high current pulse (reset programming), and to the low-resistive crystalline state using a longer pulse of lower amplitude (set programming). The parameters considered to mainly control reset switching are the reset current IR, sufficiently high to reach the melt temperature Tm of the PCM material, and the quench time tq, short enough to freeze-in the melt state. The optimization of these parameters, as demonstrated for Ge2Sb2Te5-based vertical cells in the literature (D. Mantagazza et al., 2006), (T. Nirschi et al., 2007), is thus a key to better control the switching of the cell. In the present work the influence of the pulse parameters on the reset state is investigated for a SbTe-based lateral cell. A new phenomenon affecting the resistance of the amorphous phase after reset is identified and a strong influence of the time-under-melt parameter is demonstrated.