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This paper introduces a new technique to optimally design the fractional-order Butterworth low-pass filter in the complex F-plane. Design stability is assured by incorporating the critical phase angle as an inequality constraint. The poles of the proposed approximants reside on the unit circle in the stable region of the F-plane. The improved accuracy of the suggested scheme as compared to the recently published literature is demonstrated. A mixed-integer genetic algorithm which considers the parallel combinations of resistors and capacitors for the Valsa network is used to optimize the frequency responses of the fractional-order capacitor emulators as part of the experimental verification using the Sallen–Key filter topology. The total harmonic distortion and spurious-free dynamic range of the practical 1.5th-order Butterwoth filter are measured as 0.13% and 62.18 dBc, respectively; the maximum and mean absolute relative magnitude errors are 0.03929 and 0.02051, respectively.

The formula of the all-pole low-pass frequency filter transfer function of the fractional order (N +) designated for implementation by non-cascade multiple-feedback analogue structures is presented. The aim is to determine the coefficients of this transfer function and its possible variants depending on the filter order and the distribution of the fractional-order terms in the transfer function. Optimization algorithm is used to approximate the target Butterworth low-pass magnitude response, whereas the approximation errors are evaluated. The interpolated equations for computing the transfer function coefficients are provided. An example of the transformation of the fractional-order low-pass to the high-pass filter is also presented. The results are verified by simulation of multiple-feedback filter with operational transconductance amplifiers and fractional-order element.

In this paper we propose an efficient approach to design fractional-order elements’ (FOEs) series, while using a very limited set of “seed” FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order $$\alpha $$ being in the range $$[-2,2]$$ . The proposed circuit may simply be extended to design fractional-order elements from wider range of $$\alpha $$ to follow designers’ requirements. To show the efficiency of the described technique, the use of only up to two “seed” FOEs with properly selected fractional order $$\alpha _\mathrm {seed}$$ as passive elements results in the design of a series of 17 FOEs with different $$\alpha $$ being in the range $$[-2,2]$$ . Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC.

In this paper, a new two-steps design strategy is introduced for the optimal rational approximation of the fractional-order Butterworth filter. At first, the weighting factors of the summation between the ${n}^{\text {th}}$ -order and the $(n + 1)^{\text {th}}$ -order Butterworth filters are optimally determined. Subsequently, this model is employed as an initial point for another optimization routine, which minimizes the magnitude-frequency error relative to the $(n+\alpha)^{\text {th}}$ -order, where $\alpha \in (0, 1)$ , Butterworth filter. The proposed approximant demonstrates improved performance about the magnitude mean squared error compared to the state-of-the-art design for six decades of bandwidth, but the introduced approach does not require a fractional-order transfer function model and the approximant of the $s^\alpha $ operator. The proposed strategy also avoids the use of the cascading technique to yield higher-order fractional-order Butterworth filter models. The performance of the proposed $1.5^{\text {th}}$ -order Butterworth filter in follow-the-leader feedback topology is verified through SPICE simulations and its hardware implementation based on Analog Devices AD844AN-type current feedback operational amplifier.

A detailed analysis of an operational transconductance amplifier based gyrator implementing a fractional-order inductance simulator is presented. The influence of active element non-ideal properties on the gyrator operation is investigated and demonstrated by admittance characteristics and formulas for important values and cut-off frequencies in these characteristics. Recommendations to optimize the performance of the gyrator in terms of operation bandwidth, the range of obtainable admittance magnitude, and signal dynamic range are proposed. The theoretical observations are verified by PSpice simulations of the gyrator with LT1228 integrated circuit.

This paper presents the optimal modeling of Power Law Filters (PLFs) with the low-pass (LP), high-pass (HP), band-pass (BP), and band-stop (BS) responses by means of rational approximants. The optimization is performed for three different objective functions and second-order filter mother functions. The formulated design constraints help avoid placement of the zeros and poles on the right-half s-plane, thus, yielding stable PLF and inverse PLF (IPLF) models. The performances of the approximants exhibiting the fractional-step magnitude and phase responses are evaluated using various statistical indices. At the cost of higher computational complexity, the proposed approach achieved improved accuracy with guaranteed stability when compared to the published literature. The four types of optimal PLFs and IPLFs with an exponent α of 0.5 are implemented using the follow-the-leader feedback topology employing AD844AN current feedback operational amplifiers. The experimental results demonstrate that the Total Harmonic Distortion achieved for all the practical PLF and IPLF circuits was equal or lower than 0.21%, whereas the Spurious-Free Dynamic Range also exceeded 57.23 and 54.72 dBc, respectively.

Two (α + β)-order transfer functions realizing fractional-order band-pass filter responses are presented and analysed, where 0

In this paper a concept for the efficient design of a series of floating fractional-order elements (FOEs) is proposed. Using even single or a very limited number of so-called “seed” FOEs it is possible to obtain a wide set of new FOEs featuring fractional order α being in the range [−n,n], where n is an arbitrary integer number, and hence enables to overcome the lack of commercial unavailability of FOEs. The systematic design stems from the utilization of a general immittance converter (GIC), whereas the concept is further developed by proposing a general circuit structure of the GIC that employs operational transconductance amplifiers (OTAs) as active elements. To show the efficiency of the presented approach, the use of only up to two “seed” FOEs with a properly selected fractional order αseed as passive elements results in the design of a series of 51 FOEs with different α being in the range [−2,2] that may find their utilization in sensor applications and the design of analog signal processing blocks. Comprehensive analysis of the proposed GIC is given, whereas the effect of parasitic properties of the assumed active elements is determined and the optimization process described to improve the overall performance of the GIC. Using OTAs designed in 0.18 μμm TSMC CMOS technology, Cadence Virtuoso post-layout simulation results of the GIC are presented that prove its operability, performance optimization, and robustness of the proposed design concept.

An analysis of fractional-order inductor implemented by operational transconductance amplifier (OTA)based gyrator loaded with an ideal fractional-order capacitor is presented. The impact of OTA parasitic properties on the gyrator functionality is demonstrated. The affected input admittance characteristics are included along with the relations for important values and cut-off frequencies in these characteristics. Design recommendations are provided to reduce the effect of the parasitics. The theoretical assumptions are validated by computer simulation with high-frequency model of a CMOS OTA. The constraints regarding dynamic range are also discussed.

Once designing analogue fractional-order function blocks, the capacitive and/or inductive fractional-order elements (FOEs), also referred to as constant phase elements, being defined with their fractional order $$\alpha$$ ( $$0< \alpha < 1$$ ) are required. Although currently capacitive FOEs are being discussed in the literature, still these passive elements are not readily available in discrete form and mainly do not offer the whole span of $$\alpha$$ . Therefore, to overcome such an obstacle, we primary propose the transformation of FOEs and their fractional order $$\alpha$$ to obtain the complement order $$\beta$$ , whereas $$\beta =1{-}\alpha$$ . Following the theory and mathematical description, also other transformation cases on fractional-order element are discussed and analysed in this paper. Using simple impedance converter employing single current conveyor and transconductance amplifier, the theoretical presumptions are verified both by simulations and experimental measurements.

This paper summarizes multiple cases of high-pass (HP) and band-pass (BP) analogue filter transfer functions with fractional order 1 < (1 + α) < 2. All HP and BP transfer functions are evaluated against the magnitude characteristics of ideal Butterworth responses when coefficients previously determined to approximate fractional-order (FO) Butterworth low-pass (LP) transfer functions are utilized. Comparisons of the simulated FO HP and BP responses against the ideal Butterworth responses are presented, with a least squares error analysis applied to determine the transfer functions that best approximate the Butterworth response for both HP and BP FO filters. DOI: http://dx.doi.org/10.5755/j01.eie.24.2.20634

This study presents a new realisation of voltage-mode shadow filters based on low-voltage low-power differential difference current conveyor (DDCC). Thanks to the attractive features of the DDCC, including its capability of performing arithmetic operations, the proposed filters offer the advantage of circuit simplicity, minimum number of active and passive elements, and no need for additional summing circuit, compared to the previous available shadow filter designs. The DDCC was designed and fabricated in Cadence platform using 0.35 μm CMOS AMIS process with supply voltage and power consumption of 1 V and 37 μW, respectively. The presented simulation and experimental results using a real chip validate the functionality of the proposed filters.

Novel topologies of fractional-order filters, implemented using the internal gate-source capacitance of MOS transistors, are introduced in this paper. This has been achieved using current-mirrors as active elements, resulting into resistorless realizations due to the employment of the small-signal transconductance parameter of the MOS transistor. This also offers the capability for electronic tuning of the frequency characteristics of the derived filter structures. The evaluation of the proposed technique has been performed through the design of a generalized fractional-order filter, which is also digitally programmed in such way that the four standard filter functions are offered. The behavior of the filter has been evaluated using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.

Efficient design of fractional-order elements’ (FOEs) series using a very limited set of "seed" FOEs is proposed in this paper. The proposed technique is based on an immittance converter/inverter, here using operational transconductance amplifiers. To show the efficiency of the proposed technique, using up to two "seed" FOEs with properly selected fractional order α seed results in the design of a series of 17 FOEs with different fractional order in the range [−2,2]. Simulation results are provided that show the operability of the immittance converter/inverter itself. The proposed technique can generally be simply extended to design fractional-order elements from broader range to follow the designers requirements.

This paper presents a fractional–order multiphase oscillator with adjustable FO (Frequency of Oscillation). The oscillator utilizes the following components: CCTA (Current Conveyor Transconductance Amplifier), OTA (Operational Transconductance Amplifier), auxiliary OTRA (Operational Transresistance Amplifier), two FOC (Fractional–Order Capacitors) and auxiliary resistors. The proposed structure provides three voltage outputs and their inverted variants for three selected values of $\alpha =0.3$, 0.5, and 0.8 of FOC. The FO is tuned by changing the values of the transconductances of the OTA and CCTA. The features of the presented circuit were verified by PSpice simulations with behavioural models of the active elements. Analysis of the dependence of the values of the transconductances on values of $\alpha$ and frequency is provided. A THD (Total Harmonic Distortion) and parasitic analysis of the circuit was also made.

This paper analyses the influence of fractional-order (FO) impedance element properties on characteristics of frequency filter where the element is employed. Tow-Thomas topology with one capacitor replaced by FO impedance is examined. This impedance is emulated by fifth-order Foster I network which has limited validity of FO impedance properties resulting in distortion of the filter characteristics. Shifting the frequency band of FO element emulation is tested and recommendations regarding the correct filter functionality are provided. The filter properties are also investigated from the viewpoint of characterizing the parameters of the FO impedance element connected to the filter.

Four band-pass (BP) filter transfer functions of the fractional order 1

In this paper, a fractional-order capacitor (FOC) of an order $\lambda$=0.89 (i.e. constant phase angle -80.1 degree) was emulated via Valsa RC network with five branches. The network component values were optimized using modified least squares quadratic method in a wide frequency range of 100 mHz-1kHz (i.e. 4 decades) and maximum relative phase error 0.78% was obtained. The design specification corresponds to a speed control system of an armature controlled DC motor, which is often used in control theory. Overall performance evaluation shows the product of evaluated key features (e.g. phase angle deviation and absolute values of relative phase, impedance, and pseudocapacitance errors) for the optimized FOC is 13.3% less than the one obtained via Valsa approximation. The behavior of Op-Amp-based non-inverting configurations of analogue fractional-order integral operator $s^{-\lambda}$ employing the optimized FOC, where 0

This paper introduces a new electronically controllable first-order bilinear immittance based on a single CMOS active element (voltage differencing current conveyor) and its implementation in frequency response equalization including constant phase emulation (i.e. fractional-order approximation). A cascade of current feedback operational amplifiers and grounded bilinear immittances is required for these operations. The concept brings electronic reconfigurability of parameters and simplifies also circuitry. Several application examples (equalization, fractional-order integrator/differentiator) are shown and verified experimentally with fabricated CMOS IC (C07 I2T100 0.7 μm ON Semiconductor process).

This paper presents the design and implementation of fractional-order filters based on promising CMOS structure of Differential Difference Current Conveyor (DDCC), which was designed and fabricated using the 0.35µm CMOS AMIS process. The derivation of the filters has been achieved using a second-order approximation of the corresponding fractional-order transfer functions. The filters offer the benefit of low-voltage (?500mV) operation as well as the requirement of grounded passive elements. In addition, a technique for the quick derivation of high-order filters has been introduced. The simulation and experimental results prove the attractive performances of the proposed filters.

In this paper the authors present a multifunctional reconfigurable fractional-order filter performing a low-pass, high-pass, band-pass and band-reject transfer function. The filter is based on two types of active elements, OTA (Operational Transconductance Amplifier) and ACA (Adjustable Current Amplifier). It provides pole frequency control, depending on the values of the transconductance of the OTA elements. The quality factor is also electronically controlled, depending on the amplification of the ACA element. The order of the filter can be changed by switching the fractional-order capacitor having various values of the order. The circuit was implemented as a PCB (Printed Circuit Board) and measured in laboratory conditions. Measurement results are compared with the simulation results. The behavioural models were used for the purpose of the simulation. DOI: 10.5755/j01.eie.25.1.22732

In this paper a least squares fitting is applied to determine the coefficients of a fractional-order transfer function that approximates the passband and stopband ripple characteristics of a second-order Elliptic lowpass filter. These fittings are applied to three different frequency ranges to evaluate the impact of the selection of approximated frequency band on the determined coefficients and the transfer function magnitude characteristics. MATLAB simulations of (1+ɑ) order lowpass magnitude responses with fractional steps from ɑ=0.1 to ɑ=0.9 are given as examples to highlight the fractional-step compared to the second-order Elliptic response. Further, MATLAB simulations of the (1+ɑ)=1.25 and 1.75 using all three sets of coefficients determined using different frequency bands are given as examples to highlight their differences.

This paper deals with the design, analysis, computer simulation, and experimental measurement of fractional-order sinusoidal oscillator with two current conveyors, two resistors, and two fractional immittance elements. The used conveyor is based on the bulk-driven quasi-floating-gate technique in order to offer high threshold-to-supply voltage ratio and maximum input-to-supply voltage ratio. The supply voltage of the oscillator is 1 V, and the power consumption is $$74\,\upmu \hbox {W}$$74μW, and hence the proposed oscillator can be suitable for biomedical, portable, battery-powered, and other applications where the low-power consumption is critical. A number of equations along with graphs describing the theoretical properties of the oscillator are presented. The unique features of fractional-order oscillator are highlighted considering practical utilization, element computation, tuning, phase shift of output signals, sensitivities, etc. The simulations performed in the Cadence environment and the measurements of a real chip confirm the attractive features of the proposed oscillator.

Besides frequency filters being designed to feature specific and fixed parameters, filters with dynamically adjustable transfer function are also required in signal processing. Understanding the fractional-order α as a new controllable parameter of the fractional-order filters, the concept of arbitrarily adjustable analog frequency filters is proposed and discussed in detail within this chapter. The general transfer functions are presented that feature the possibility of adjusting one or even all of a filter’s parameters by means of passive components and/or particular parameters of active elements used to implement the circuit. Based on the described transfer functions, the general topologies of the function systems are presented that are used as initial for the design of fractional-order frequency filters employing required types of active elements. As a result, the simplest and most minimal in configuration circuit solutions can be synthesized that fully follow the designer’s initial requirements on a filter’s parameter(s) adjustability and tunability. To show the use of the theoretical presumptions, the fractional-order low- and high-pass filters are designed, where operational transconductance amplifiers and adjustable current amplifiers are advantageously employed to introduce the electronic control and adjustment of the filter parameters.

Using current conveyors, we present six different current-mode circuits approximating fractional-order low-pass transfer function. Proposed circuits always use four active elements, three capacitors and seven or five resistors, whereas all are grounded. We show that the usage of only eight passive elements is sufficient to approximate a (1 + α)-order system (0 < α < 1) and can even provide better performance. The performance of the circuits is analysed evaluating the relative errors in magnitude and phase.

Using the theory of analyzing the properties of RC-EDP (resistive-capacitive elements with distributed parameters) structures we propose the synthesis of elements with fractional impedance (EFI) — fractional capacitors C α (0 < α < 1) suitable for analogue function block design. The direct utilization of such fractional elements overcomes the problem of approximating the needed fractional order element by an RC ladder or any other similar structure or approximating the fractional transfer function by an integer-order one. For the EFI synthesis, a genetic algorithm based tool has been developed that based on the required properties of the EFI to be designed determines the parameters of individual R-C-NR sections and their interconnection, whereas the parasitic parameteres relevant for the implementation process can also be assumed. Using the outputs of the software, we show the further usage of the R-C-NR section's parameters resulting in the layout design of the final fractional capacitor.

This paper presents a new electronically tunable voltage-mode quadrature oscillator using two high performance current controlled current differencing buffered amplifiers (CCCDBA), two capacitors and single resistor, all of them are grounded which is advantageous for monolithic integration. The condition of oscillation and the frequency of oscillation are independent and can be controlled by two separate bias currents. The output voltages are obtained at the terminals with almost zero internal impedances, thus there is no need to use any buffering devices. The MOS structure of the CCCDBA presented in this paper is of a high performance and ensures precision, large dynamic range, wide bandwidth and has the capability to drive a load with very low resistance. Non-ideal analysis of the proposed oscillator is provided and PSpice simulation results using the 0.18 μm n-well CMOS technology from TSMC are included to verify the correct functionality of the proposed circuit.

Recently, the demand for low-voltage low-power integrated circuits design has grown dramatically. For battery-operated devices both the supply voltage and the power consumption have to be lowered in order to prolong the battery life. This paper presents an attractive approach to designing a low-voltage low-power high-precision differential-input buffered and external transconductance amplifier, DBeTA, based on the bulk-driven technique. The proposed DBeTA possesses rail-to-rail voltage swing capability at a low supply voltage of ±400 mV and consumes merely 62 μW. The proposed circuit is a universal active element that offers more freedom during the design of current-, voltage-, or mixed-mode applications. The proposed circuit is particularly interesting for biomedical applications requiring low-voltage low-power operation capability where the processing signal frequency is limited to a few kilohertz. An oscillator circuit employing a minimum number of active and passive components has been described in this paper as one of many possible applications. The circuit contains only a single active element DBeTA, two capacitors, and one resistor, which is very attractive for integrated circuit implementation. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the unique results.

In this paper, a novel low-voltage ultra-low-power class AB current conveyor of the second generation based on folded cascode operational transconductance amplifier OTA with floating-gate differential pairs is presented. The main features of the proposed conveyor are design simplicity and rail-to-rail input voltage range at a low supply voltage of ±0.5 V. The proposed conveyor has a reduced power consumption of only 10 μW. Due to these features, the proposed conveyor could be successfully employed in a wide range of low-voltage low-power analog signal processing applications. PSpice simulation results using the 0.18 μm CMOS technology from TSMC are included to prove the results. As an example of application, a current-mode quadrature oscillator is designed and its functionality is proved by simulation.

This paper presents possible approaches to the design of a novel low-voltage, low-power, and high-precision current conveyor of the second generation (CCII+/-) based on the bulk-driven folded cascode operational transconductance amplifier (OTA) with extended input common-mode voltage range. This CCII+/- utilizes bulk-driven differential pairs to obtain a nearly rail-to-rail input stage at a low supply voltage. The proposed conveyor operates at a low supply voltage of +/-400mV with a reduced power consumption of only [email protected] A current-mode multifunction filter is presented as an application of the CCII+/-. This filter provides five transfer functions simultaneously, namely low-pass, band-pass, high-pass, notch, and all-pass. The filter has the following properties and advantages: it employs three bulk-driven current conveyors BD-CCII+/-, three grounded resistors, and two grounded capacitors, which is suitable for integrated circuit implementation. Furthermore, the input signal is connected to the low-impedance X terminal of the BD-CCII+/- whereas the output signals are taken from the high-impedance output terminals Z+ and Z-. Finally, the pole frequency and quality factor of the designed filter are tunable independent of each other. PSpice simulation results using the [email protected] CMOS technology are included to prove the results.

The paper describes a new method for the classification of digital modulations. ASK, 2FSK, 4FSK, MSK, BPSK, QPSK, 8PSK and 16QAM were chosen for recognition as best known digital modulations used in modern communication technologies. The maximum value of the spectral power density of the normalized-centered instantaneous amplitude of the received signal is used to discriminate between frequency modulations (2FSK, 4FSK and MSK) on one hand and amplitude and phase modulations (ASK, BPSK, QPSK, 8PSK and 16QAM) on the other hand. Then the 2FSK, 4FSK and MSK modulations are classified by means of spectrums. The histograms of the instantaneous phase are used to discriminate between ASK, BPSK, QPSK, 8PSK and 16QAM. The method designed was tested with simulated and measured signals corrupted by white Gaussian noise.

This article analyzes parallel resonant circuit containing fractional capacitor and inductor. Relations for complex impedance, resonant frequency, and resistance at this frequency are derived. These formulas are then expressed graphically. The influence of the exponents of frequency dependence of impedance a and β is especially emphasized which is not present when classical elements are used. The possibilities of practical implementation of fractional elements are introduced whereas RC elements with distributed parameters are preferred. An example of fractional capacitor made by thick-film technology is shown and rules for finding its parameters are stated.