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Your search keyword '"Dao, V. T. S."' showing total 16 results
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16 results on '"Dao, V. T. S."'

10. Evaluation of a backside-illuminated ISIS

Author

Nguyen, H. D., primary, Vo-Le, C., additional, Dao, V. T. S., additional, Takehara, K., additional, Etoh, T. G., additional, Kondo, Y., additional, Maruno, H., additional, Tominaga, H., additional, Soya, H., additional, van Kuijk, H., additional, Bosiers, J., additional, Klaassens, W., additional, Ingram, G., additional, Singh, S., additional, and Lesser, M., additional

Published
2008
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13. A Backside-Illuminated Image Sensor With 200 000 Pixels Operating at 250 000 Frames per Second.

Author

Cuong Vo Le, Etoh, T. Goji, Nguyen, H. D., Dao, V. T. S., Soya, H., Lesser, Michael, Ouellette, David, Kuijk, H. van, Bosiers, J., and Ingram, G.

Subjects
IMAGE quality in imaging systems, IMAGE converters, LIGHTING, ELECTRONIC noise, PIXELS, OPTICAL resolution, DIGITAL image processing
Abstract

In this paper, a high-speed image sensor with very high sensitivity is developed. The high sensitivity is achieved by introduction of backside illumination and charge-carrier multiplication (CCM). The high frame rate is guaranteed by installing the in situ storage image sensor (ISIS) structure on the front side. A test sensor of the BSI-ISIS has been developed and evaluated: It is shown that an image with a very low signal level embedded under the noise floor is recognizable by activating the CCM. [ABSTRACT FROM AUTHOR]

Published
2009
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14. Pixel parallel localized driver design for a 128 x 256 pixel array 3D 1Gfps image sensor

Author

Etoh, T. Goji, Shiraga, Hiroyuki, Zhang, C., Dao, V. T. S., Etoh, T. G., and Charbon, E.

Subjects
Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY
Abstract

In this paper, a 3D 1Gfps BSI image sensor is proposed, where 128 × 256 pixels are located in the top-tier chip and a 32 × 32 localized driver array in the bottom-tier chip. Pixels are designed with Multiple Collection Gates (MCG), which collects photons selectively with different collection gates being active at intervals of 1ns to achieve 1Gfps. For the drivers, a global PLL is designed, which consists of a ring oscillator with 6-stage current starved differential inverters, achieving a wide frequency tuning range from 40MHz to 360MHz (20ps rms jitter). The drivers are the replicas of the ring oscillator that operates within a PLL. Together with level shifters and XNOR gates, continuous 3.3V pulses are generated with desired pulse width, which is 1/12 of the PLL clock period. The driver array is activated by a START signal, which propagates through a highly balanced clock tree, to activate all the pixels at the same time with virtually negligible skew.

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