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X-ray lithography has been used in mix and match mode with optical steppers to build test circuits in support of DRAM and Logic development at IBM's Advanced Semiconductor Technology Center, ASTC. Prior to building the test devices, hundreds of wafers were exposed using x-ray lithography to define the etch processes for critical levels and to help separate optical lithography, resist and etching effects. The demand for this type of support required IBM's Advanced Lithography Facility (ALF) to focus on a set of pilot line issues not previously faced by this emerging lithography. The challenges and solutions which resulted are discussed. This paper examines the requirements for the introduction of x-ray into pilot line use based on ALF's most recent experience and performance.

We report on an IC lithographic resolution study in which APEX-E resist on polysilicon coated wafers was exposed to synchrotron x radiation through a high-resolution mask that contained Au-electroplated features ranging in size from 0.5 down to 0.15-micrometers . Exposures were made at mask-to-substrate gaps ranging from 20 to 35 micrometers and at doses from 100 to 134 mJ/cm2. We probed the wafers with an SEM, both before and after etch, and electrically. From the electrical linewidth probing, we found that for isolated lines and 1:2 L:S patterns the feature widths were linear down to 0.18-micrometers . For the 1:1 and 2:1 L:S arrays, the widths were linear down to 0.25-micrometers . Dense and isolated lines down to 0.25-micrometers exhibited +/- 15% dose latitude over a 10-micrometers gap range. Contact holes were examined only by SEM. The smallest size that printed was nominally 0.225 micrometers , but was measured to be 0.20-micrometers after etch. Critical dimension uniformity, calculated with each feature type allowed its own mean value, was approximately equals 40 nm (3(sigma) ), including intrafield and across wafer variation. The mask CD uniformity was approximately equals 30 nm (mean + 3(sigma) ). The wafer-to-wafer CD variation was found to be 6 nm (3(sigma) ) and the electrical test-to-test CD variation was 3 nm (3(sigma) ). We use regression analysis to separate the component of CD variation that is assignable to intrafield form that assignable to interfield. The regression analysis to separate the component of CD variation that is assignable to intrafield from that assignable to interfield. The regression analysis indicates that these components of CD variation are systematic rather than random. The main contributor to the interfield component may be polysilicon etch. The intrafield error is believed to be caused predominantly by beamline nonuniformity and not by errors on the 1x mask.

The synchrotron x ray lithography (XRL) project described was conducted as a learning and feasibility vehicle for gate level lithography in support of IBM's most advanced CMOS logic programs. An electrically probable multilevel lithography test site was developed and characterized to exercise critical design, mask manufacture, alignment, exposure, and metrology issues in the 150 - 350 nm linewidth range. A fully capped silicided polysilicon gate stack was chosen for the electrical measurements in order to develop and demonstrate the XRL and related reactive ion etch process on a realistic, product-like substrate. This paper addresses test site design issues, elaborates on the mask manufacturing process, and presents SEM and electrical data from wafers processed at IBM's Advanced Semiconductor Technology Center. The data presented demonstrate the feasibility of supporting early device development and process integration with XRL and highlight the need for high resolution, defect free, proximity corrected masks to fully exploit the capabilities of x ray lithography.

A joint Motorola/IBM experiment was performed in mix-and-match lithography across widely separated locations. A simple pattern placement metrology data set was created, and x-ray masks were manufactured according to this data. The same data was converted into a 5x reticle and optically stepped on wafers. The x-ray mask was designed to print upon two optical fields with one x-ray exposure. The x-ray mask was aligned to the wafers to produce box-in- box images for overlay metrology. The main overlay problems encountered were systematic offsets between x-ray and optical images, and average magnification error of approximately 8 ppm. The magnification error is substantial because of the 3 degree(s)C temperature difference between the optical stepper stage and the x-ray mask-writer. In an actual device run, the magnification differences will be removed by compensation in the e-beam writing of the x-ray mask. Offsets will be removed by use of a send-ahead wafer to determine the correct offset alignment in the x-ray stepper.