390 results on '"Daniel Grosse"'
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2. Towards a Highly Interactive Design-Debug-Verification Cycle.
3. Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing.
4. Relation Coverage: A New Paradigm for Hardware/Software Testing.
5. A RISC-V 'V' VP: Unlocking Vector Processing for Evaluation at the System Level.
6. Using Formal Verification Methods for Optimization of Circuits Under External Constraints.
7. WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL.
8. Introduction to the Special Issue on Specification and Design Languages (FDL 2021).
9. Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis.
10. GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development.
11. SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs.
12. Formal Verification of SUBLEQ Microcode implementing the RV32I ISA.
13. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing.
14. RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V.
15. WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging.
16. An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle.
17. Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization.
18. Verifying SystemC TLM peripherals using modern C++ symbolic execution tools.
19. Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability.
20. Improving Design Understanding of Processors leveraging Datapath Clustering.
21. RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal.
22. Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV.
23. Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level.
24. EPEX: Processor Verification by Equivalent Program Execution.
25. XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding.
26. System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations.
27. Mutation-based Compliance Testing for RISC-V.
28. System Level Verification of Phase-Locked Loop using Metamorphic Relations.
29. Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization.
30. Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study.
31. Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling.
32. Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes.
33. Early Verification of ISA Extension Specifications using Deep Reinforcement Learning.
34. Towards Generation of a Programmable Power Management Unit at the Electronic System Level.
35. Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime.
36. ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks.
37. Towards Specification and Testing of RISC-V ISA Compliance⋆.
38. Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*.
39. Towards Formal Verification of Optimized and Industrial Multipliers.
40. Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning.
41. RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms.
42. Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes.
43. Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*.
44. Verification for Field-coupled Nanocomputing Circuits.
45. Toward RISC-V CSR Compliance Testing.
46. Waveform-based performance analysis of RISC-V processors: late breaking results.
47. Systematic RISC-V based Firmware Design⋆.
48. Functional Coverage-Driven Characterization of RF Amplifiers.
49. (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs.
50. Automated Analysis of Virtual Prototypes at Electronic System Level.
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