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This paper showcases a passive single side-band (SSB) subharmonically pumped (SHP) GaN on Si mixer intended for operation in the Ku band. A passive topology has been selected in order to test the viability of these kinds of designs for GaN applications. By utilising the SSB SHP mixer, it is possible to reduce the energy consumption of a complete transmission system implementation. Two techniques to enhance the performance of the mixer are tested. First, the quasi-lumped method has been employed to reduce the size of the stubs needed to implement the mixer topology. Secondly, octagonal tapered inductors were used to obtain higher quality factors and narrow the frequency response of the lumped-element hybrids. The final design occupies an area of 2720 μ m × 1514 μ m , including pads. Measurements show a performance in line with the simulations, with a slight increase in its losses with respect to the simulation results. Through the measurement of a transistor of the technology, it is demonstrated that this deviation is caused by the variability of the process and its low technology readiness level (TRL). The results are very promising and prove the advantages of implementing passive mixers for high-frequency applications in GaN on Si technologies.

A fully integrated dual-band low noise amplifier (LNA) is presented. The proposed circuit combines a wideband input impedance matching with switched resonant circuits' loads at the output. As the tuning mechanism is placed at the output of the LNA and no input reconfiguration is needed, the noise contribution is minimized. Experimental results from a test chip prototype in BiCMOS 0.35-µm technology are shown that validate the proposed circuit. The designed two-band amplifier provides a gain of 13 and 11 dB at 1.8 and 2.4 GHz, respectively, with a noise figure of 3.8 and 4.1 dB while drawing 16 mW from a 3.3-V supply. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2107–2110, 2014

In this work, the package influence on a feedback low-noise amplifier has been studied.The electromagnetic simulator of ADS was used to obtain the QFN16 package model and the bonding model. The influence of the package and the pad on the supply node was negligible when it was studied separately. However, the circuit performance is reduced when the inductance introduced by the bonding of the supply node is combined with the parasitic capacities associated to the pad with electrostatic discharge protection. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1435–1440, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27601

A low noise amplifier scheme to achieve low-voltage and wide-bandwidth operation is presented. This circuit is based on folded cascode topology combined with wideband impedance matching and shunt peaking load. One of the drawbacks of the proposed scheme is that it uses more area than the conventional cascode due to the two additional inductors and capacitors to implement the capacitively coupled LC tanks. To reduce the area of the circuit, we have used stacked inductors, a brief study of these kinds of inductors is presented. Two low noise amplifiers have been fabricated using a mature 0.35 μm BiCMOS technology, one using the cascode conventional approach and the other using the proposed topology. Measurement results show that for the same transistors operating conditions, the low-voltage amplifier performance is similar than the conventional cascode. By virtue of the small area of stacked inductors, the size of both low noise amplifiers is comparable. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2495–2500, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25530

This paper presents a tutorial on RF and mixed signal circuits design for a digital video broadcasting-handheld tuner. A detailed description of the wideband low noise amplifier, the mixer, the synthesizer and the ADC, which are the most challenging components of a receiver, are carried out. Requirements relative to frequency range, sensitivity, noise figure, linearity, phase noise gain and dynamic range are discussed. The LNA uses a cascode configuration, combining a resistive loaded LNA with a conventional resistive shunt-feedback, in order to achieve a low power, low noise and wide bandwidth. The mixer uses a classical Gilbert cell configuration. The VCO employs techniques like emitter degeneration, capacitor divider, and optimum bias for minimum noise to improve phase noise requirements and oscillation amplitude. There are two ADC structures, one of which is a delta sigma ADC. The blocks are implemented in a AMS 0.35 μm BiCMOS process.

This paper presents an 868 MHz wake-up radio using uncertain-IF architecture for wireless sensor network. It is designed to receive data modulated with on-off-keying in UMC 65nm CMOS technology and it employs uncertain-IF architecture to reduce the oscillator design constraints and to decrease power consumption. The wake-up radio consist of a single-ended active mixer, a five stage IF-amplifier and a differential envelope detector biased in weak inversion. The wake-up radio has been designed with to provide a trade-off between sensitivity and power consumption. The obtained sensitivity and power consumption is −78 dBm and 40.9 µW, respectively, with 1.2 V power supply.

In this paper different alternatives of wake-up receiver in ultra-low power wireless sensor nodes are studied. The limitations of power dissipation, area or cost require a holistic approach to the problem, taking into account every stage of design such as the architecture and the radio frequency sub-system. Reduce data communication only when necessary can be achieved using two radios, one for standard communication as transceiver and another devoted to wake-up receiver. The wake-up receiver listens the input signal to detect the addressed bit sequence. This work deals with the wake-up receiver design of different architectures. A comparison of the trade-off between them is performed. In each case characteristics such as sensitivity or distances with low power consumption are exposed. The input signal of the wireless sensor node is a 125 kHz on-off keying modulated at 868 MHz and the circuits are designed to operate in 868 MHz band. A first option is used a tuned radio frequency architecture with a discrete detector with Schottky diode to demodulates the OOK signal. The following structure is with an envelope detector where the envelope detector is designed in weak inversion to have a low consumption. Is possible improve the voltage gain including an impedance matching in the input of the detector. Other option is including an amplifier before the detector to improve detector sensitivity. The amplifier with active inductor has to be in subthreshold region to have moderate power consumption. The circuits are designed in UMC CMOS 65 nm technology with 1.2 V supply.

In this paper different parts of a wake-up receiver for wireless sensor node are presented. The circuit is composed of an amplifier with input impedance matching network and an envelope detector both working at 868 MHz. The amplifier is incorporated in order to increase the sensitivity of the wake-up receiver. The amplified signal passes to the envelope detector which demodulate on-off keying signal at 125 kHz. The circuits have been designed to optimize power consumption and area. The total power consumption and the minimum signal detected are 44.32 uW and 0.4 mVp respectively. The circuits were implemented in UMC CMOS 65 nm process.