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The perpendicular-spin-transfer-torque magnetic-tunnel-junction neuron exhibited integrate behaviour depending on the nanoscale grain size of the MgO tunnelling barrier showing possibility for spiking neural network applications.

The learning and inference efficiencies of an artificial neural network represented by a cross-point synaptic memristor array can be achieved using a selector, with high selectivity (I

Abstract Spiking neurons communicate with other neurons using sparse and binary signals in a human brain, so they can achieve real-time processing of the information with ultra-low power consumption[1,2]. Thereby, spiking neurons are essential elements for building an energy-efficient biomimetic spatiotemporal system. Recently, to emulate the behavior of biological neuron, many researches for memristive device-based neurons with peripheral circuits (i.e., sense-amplifier or reset circuit)[3] and complementary metal-oxide-semiconductor (CMOS) neurons with capacitors have been reported[4]. Most of the reported memristive device-based neurons required a high operation voltage (>1.2 V) for emulating integrate function of a biological neuron. In addition, complementary metal-oxide-semiconductor-based neurons could not achieve high neuronal density due to using a capacitor in emulating integrate function. In this study, therefore, we propose an electrochemical metallization cell based memristive neuron chip fabricated with 28-nm CMOS process having a low operation voltage ( Acknowledgement This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT(2021M3F3A2A01037733). Reference Mead, C. Neuromorphic Electronic Systems. Encycl. Comput. Neurosci. 78, 1979–1979 (2015). Douglas, R. Neuromorphic Analogue VLSI. Annu. Rev. Neurosci. 18, 255–281 (1995). Tuma, T., Pantazi, A., Le Gallo, M., Sebastian, A. & Eleftheriou, E. Stochastic phase-change neurons. Nat. Nanotechnol. 11, 693–699 (2016). Aamir, S. A., Müller, P., Hartel, A., Schemmel, J. & Meier, K. A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic system. Eur. Solid-State Circuits Conf. 2016-Octob, 71–74 (2016). Figure 1

Corresponding to the principles of biological synapses, an essential prerequisite for hardware neural networks using electronics devices is the continuous regulation of conductance. We implemented artificial synaptic characteristics in a (GeTe/Sb2Te3)16 iPCM with a superlattice structure under optimized identical pulse trains. By atomically controlling the Ge switch in the phase transition that appears in the GeTe/Sb2Te3 superlattice structure, multiple conductance states were implemented by applying the appropriate electrical pulses. Furthermore, we found that the bidirectional switching behavior of a (GeTe/Sb2Te3)16 iPCM can achieve a desired resistance level by using the pulse width. Therefore, we fabricated a Ge2Sb2Te5 PCM and designed a pulse scheme, which was based on the phase transition mechanism, to compare to the (GeTe/Sb2Te3)16 iPCM. We also designed an identical pulse scheme that implements both linear and symmetrical LTP and LTD, based on the iPCM mechanism. As a result, the (GeTe/Sb2Te3)16 iPCM showed relatively excellent synaptic characteristics by implementing a gradual conductance modulation, a nonlinearity value of 0.32, and 40 LTP/LTD conductance states by using identical pulse trains. Our results demonstrate the general applicability of the artificial synaptic device for potential use in neuro-inspired computing and next-generation, non-volatile memory.

The temperature uniformity of heater plates (HPs) should be sustained due to critical dimension uniformity and robust operation in high temperature processing of 300 mm wafers. It is very challenging to maintain the temperature uniformity of the HP despite the dynamic control of power inputs and temperatures. The packaged power terminals (PPTs) of the HPs may considerably affect their thermal reliability. Hence, the sophisticated thermal modellings and designs of the HPs and the PPTs are necessary. In this study, the finite element analysis (FEA) thermal models of the HP and the PPT were generated, experimentally validated, and employed for the analysis and the design. The influences of the heating element width, the heating element gap, and the zone gap on the thermal performance of the HP were investigated. The parametric influences of the substrate thickness on the thermal performance of the PPT were also explored. The results show that the effect of the heating element width on the temperature of the HP is almost negligible. The results have found that a sophisticated design of the heating elements may reduce the radial temperature difference of the HP by 56 % compared with the baseline case. The results suggest that the sophisticated design may enable both the simplified structure and the enhanced temperature uniformity of the HP.

Abstract Recently, the demand for more data storage and fast processing has been dramatically increased for the big data markets such as artificial intelligence (AI), virtual reality (VR), autonomous car, and internet of things (IoT). Thus, a new memory such as a storage class memory (SCM) has been introduced since it can perform a reasonable latency compared to DRAM and a lower bit-cost than NAND flash memory [1]. Remind that, generally, a SCM has been fabricated with three-dimensional cross point memory cell array [2]. As a candidate memory cell for SCM, resistive-random-access-memory (ReRAM) has been proposed; i.e., called storage-type SCM. Santini, C. A. et al. demonstrated amorphous carbon oxide (a-COx) based ReRAM-cell having a reasonable memory window margin (I on/I off > 100), a fast switching speed of 20~50 ns at ~ 100-nm-diameter memory cell size. However, it showed extremely a high forming voltage (V forming) of ~ 5.0 V and a high reset voltage (V reset) of ~ – 4.0 V [3]. In particular, the a-COx based ReRAM-cell presented a different bi-stable memory characteristic for another typical ReRAM-cells; i.e., its bias directions of set and reset were opposite to a typical ReRAM, which mechanism was not evidently proved. In addition, the forming process for this ReRAM cell would be highly undesirable since it caused an extra burden for initializing memory-cells and degraded the write and erase endurance cycles [4]. Here, for the first time, we designed a forming-free Cu-doped amorphous-carbon-oxide based ReRAM cell, which did not need a forming process and we reviewed the memory operation mechanism by understanding electrical and chemical properties of the Cu-doped a-COx based ReRAM cells. A typical a-COx based ReRAM-cell needed a forming process; i.e., a forming voltage of – 2.20 V and a set voltage of – 1.05 V, as shown in Fig. 1 (a). Otherwise, a Cu-doped a-COx based ReRAM-cell could achieve a forming-free process; i.e., a forming voltage (i.e. - 0.85 V) was the same as a set voltage (i.e. – 0.85 V), as shown in Fig. 1 (b). In addition, it demonstrated a write and erase endurance cycles of ~106 by sustaining a memory margin of ~1.3×102, being able to be utilized for a commercial nonvolatile memory-cell, as shown in Fig. 1(c). To clarify the forming-free mechanism, the depth profiles of C, Cu, and O atom in the Cu-doped a-COx memory cell were observed in detail under pristine, after set, and after reset process, which were obtained from intensity line-profiles of EELS/EDS elemental mapping images at C-K edges, O-K edges, Cu-Kα, Pt-La1, and W-La1. For the pristine state, C, Cu, and O atoms are uniformly distributed in the Cu-doped a-COx layer, as shown in Fig. 1(d). In addition, after a set process, since a negative voltage was applied to the top Pt electrode, Cu atoms evidently moved and segregated toward the top Pt electrode, as shown in a of Fig. 1(e), while O atoms evidently migrated and pile up toward the bottom W electrode, as shown in b of Fig. 1(e). This result means that the conductive C-C sp2 filaments in the Cu-doped a-COx layer were produced when oxygen atoms migrated and piled up toward bottom W electrode and the conductive Cu-atom filaments were formed in the Cu-doped a-COx layer since Cu atom moved and segregated toward the top Pt electrode. Hence, both conductive C-C sp2 filaments and Cu-atom filaments were generated simultaneously in the Cu-doped a-COx layer, achieving a set process without a forming process. On the other hand, after a reset process, since a positive voltage was applied to the top Pt electrode, Cu and O atoms were redistributed inside the Cu-doped a-COx, resulting in breaking both C-C sp2 filaments and Cu-atom filaments, as shown in a and b of Fig. 1(f). In our presentation, we will demonstrate and review the mechanisms between a set process without forming process and a reset process in detail by electrical and chemical composition depth profiles depending on the applied bias condition. In particular, we will demonstrate a different ReRAM behavior of the Cu-doped a-COx based ReRAM from a typical ReRAM or CBRAM. Acknowledgement This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055). Reference [1] Matsui, C. et al. Integration 2019, 69, 62-74. [2] Hady, F. T. et al. Proceedings of the IEEE 2017, 105, (9), 1822-1833. [3] Santini, C. A. et al. Nature Communications 2015, 6, (1), 8600. [4] Skaja, K. et al. Scientific Reports 2018, 8. Figure 1

Recently, memristive devices (e.g. CBRAM and ReRAM etc.) have been proposed as an alternative to C-MOSFET based neuromorphic device (i.e. neuron and synapse) to achieve a high neuronal density and low power consumption. Among memristive devices, the conductive bridge neuron has been a great attention due to its area efficiency, low power consumption (< 500 fJ), and good C-MOS compatibility 1-3 . However, past researches have mainly focused on stochastic nature of conductive-bridge neurons. In particular, most of the stochastic conductive-bridge neuron have used capacitors to implement membrane potential, which requires a large integration area (~1000F2). In this works, integrate property of Al2O3-based cap-less conductive-bridge neuron was demonstrated which allows a cost-efficient neuromorphic chip by using a same process technology as a memristor synapse, as shown in Fig 1 (a). Note that the Al2O3-based cap-less conductive-bridge neuron was the same as that of the Al2O3-based memristor synapse. In addition, we investigated the effect of negative-differential-resistance (NDR) characteristic on integrate property for our proposed neuron, depending on the compliance current level (i.e. a shape of metallic filaments in neuron device). The NDR slope was adjusted by varying a compliance current of a Al2O3-based cap-less conductive-bridge neuron. The current compliance (Icc) of 1 mA showed the NDR slope of ~ 0.56 decade/V, as shown in Fig. 1(b). For all spike amplitude (i.e. -0.6~-1.0 V), the resistances of neuron device abruptly increased at a certain number of spikes, depending on the spike amplitude, and then it gradually increased with the number of spikes, as shown in Fig. 1(c). In addition, the spike number being necessary for achieving ~600 Ω decreased exponentially with increasing the number of spikes, as showed integrate property depending on input spike amplitude, as shown in Fig. 1(d). Otherwise, the current compliance (Icc) of 0.1 mA, which was 10 times less than Fig 1 (b) presented the NDR slope of ~ 0.23 decade/V, which was 2 times less than Fig. 1(b), as shown in Fig. 1(e). For all spikes amplitude, the resistance of neuron devices gradually increased with the number of spikes, wherein the resistance of neuron devices increased with the spike amplitude (i.e. negative voltage pulse amplitude), as shown in Fig. 1(f). The spike number being necessary for achieving ~10 kΩ decreased exponentially with increasing the number of spikes, as shown in Fig. 1(g). Comparing Fig. 1(d) with Fig. 1(g), the variation of the spike number being necessary for achieving ~600 Ω for the NDR slope of ~-0.56 decade/V was much less that for the spike number being necessary for achieving ~10 kΩ for the NDR slope of ~-0.23 decade/V. This result indicates that, for the Al2O3-based cap-less conductive-bridge neuron, the NDR slope dominantly determines the integrate nature. In our presentation, we will discuss the mechanism why the integrate property depended on the NDR slope via understanding a shape of conductive-metallic-filaments in Al2O3 layer, which determine an integrate property of neuron devices. In particular, it will be reported that the shape of conductive-metallic-filaments strongly depended on the metal vacancy concentration in binary oxide (i.e. Al2O3) layer. Acknowledgement This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) (No. 2016M3A7B4910249). Reference "IEEE Transactions on Emerging Topics in Computational Intelligence," in IEEE Transactions on Emerging Topics in Computational Intelligence, vol. 2, no. 5, pp. C2-C2, Oct. 2018, doi: 10.1109/TETCI.2018.2867377. Jang, B. Attarimashalkoubeh, A. Prakash, H. Hwang and Y. Jeong, "Scalable Neuron Circuit Using Conductive-Bridge RAM for Pattern Reconstructions," in IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2610-2613, June 2016, doi: 10.1109/TED.2016.2549359. Palma, M. Suri, D. Querlioz, E. Vianello and B. De Salvo, "Stochastic neuron design using conductive bridge RAM," 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Brooklyn, NY, 2013, pp. 95-100, doi: 10.1109/NanoArch.2013.6623051. Figure 1

Failures may often occur in the packaged power terminals (PPTs) of the heater modules during harsh wafer baking process. The dominant failure factor is a high temperature. Hence, the performances of the PPTs should be explored under multiphysics environment to develop robust heater modules. In this study, FEA electrical-thermal-structural models of the PPTs are developed and experimentally validated. Various parametric influences on the thermal and structural performance of PPTs are investigated employing FEA electrical-thermal-structural models. The study has shown that the substrate thickness was a dominant parameter affecting the PPT performance.