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The computing industry is rapidly moving from a programming to a learning area, with the reign of the von Neumann architecture starting to fade, after many years of dominance. The new computing paradigms of non-von Neumann architectures have started leading to the development of emerging artificial neural network (ANN)-based analog electronic artificial intelligence (AI) chipsets with remarkable energy efficiency. However, the size and energy advantages of electronic processing elements are naturally counteracted by the speed and power limits of the electronic interconnects inside the circuits due to resistor-capacitor (RC) parasitic effects. Neuromorphic photonics has come forward as a new research field, which aims to transfer the well-known high-bandwidth and low-energy interconnect credentials of photonic circuitry in the area of neuromorphic platforms. The high potential of neuromorphic photonics and their well-established promise for fJ/Multiply-ACcumulate energy efficiencies at orders of magnitudes higher neuron densities require a number of breakthroughs along the entire technology stack, being confronted with a major advancement in the selection of the best-in-class photonic material platforms for weighting and activation functions and their transformation into co-integrated photonic computational engines. With this paper, we analyze the current status in neuromorphic computing and in available photonic integrated technologies and propose a novel three-dimensional computational unit which, with its compactness, ultrahigh efficiency, and lossless interconnectivity, is foreseen to allow scalable computation AI chipsets that outperform electronics in computational speed and energy efficiency to shape the future of neuromorphic computing. [ABSTRACT FROM AUTHOR]

Herein, we present a design analysis and optimization of open-cladded plasmonic waveguides on a Si3N4 photonic waveguide platform targeting CMOS-compatible manufacturing. For this purpose, two design approaches have been followed aiming to efficiently transfer light from the hosting photonic platform to the plasmonic waveguide and vice versa: (i) an in-plane, end-fire coupling configuration based on a thin-film plasmonic structure and (ii) an out-of-plane directional coupling scheme based on a hybrid slot waveguide. A comprehensive numerical study has been conducted, initially deploying gold as the reference metal material for validating the numerical models with already published experimental results, and then aluminum and copper have been investigated for CMOS manufacturing revealing similar performance. To further enhance coupling efficiency from the photonic to the plasmonic part, implementation of plasmonic tapering schemes was examined. After thorough investigation, plasmo-photonic structures with coupling losses per single interface in the order of 1 dB or even in the sub-dB level are proposed, which additionally exhibit increased tolerance to deviations of critical geometrical parameters and enable CMOS-compatible manufacturing. [ABSTRACT FROM AUTHOR]

We demonstrate two 8 × 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/ demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being ~12 and ~9 ~m, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 μW/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than ~18 dB crosstalk and higher than ~40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 X 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proofof- concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties. [ABSTRACT FROM AUTHOR]