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The ten-switch inverter is recently proposed in the literature to replace the neutral clamped point three-level inverter; it can produce a two/three-level output voltage using only ten switches. The conventional modulation strategies generate a large common mode voltage (CMV), which increases the leakage current. The use of the sinusoidal pulse width modulation (SPWM) produces a high CMV of Vdc/2. On the other hand, using conventional space vector modulation (SVM) methods can only reduce the CMV to Vdc/3. To achieve further reduction in the magnitude of the CMV, a new virtual SVM (VSVM) strategy is suggested. The space vector diagram is constructed with virtual vectors which can generate the lowest possible CMV (|VCM|= Vdc/6). In the proposed VSVM, the action times are calculated and the switching sequence is synthesized for each region. The VSVM is applied to a ten-switch inverter through a simulation, and it is validated experimentally. It is compared to some existing modulation techniques, such as the SPWM method, two SVM methods and the conventional VSVM. Simulation and experimental results showed that the proposed VSVM algorithm can effectively reduce CMV to Vdc/6. The use of virtual vectors does not affect the performance of the proposed algorithm in terms of the use of the DC bus voltage. In addition, it can effectively balance the neutral point voltage. However, the analysis of voltages and currents demonstrated that the use of virtual vectors increases the rate of harmonics compared to conventional SVM methods. [ABSTRACT FROM AUTHOR]

This paper introduces the multi-neighboring reference vector discontinuous pulse-width modulation (MNRV DPWM) with offset voltage injection methodology tailored for single-phase diode-clamped four-level PWM inverters. By evenly utilizing multiple adjacent reference vectors with diverse charging/discharging characteristics of dc-link capacitors and employing duty compensators to adjust minor voltage discrepancies under practical conditions, precise tracking of commanded voltages is ensured even under transient conditions, while maintaining balanced voltages across the dc-link capacitors. This approach proposes various continuous/discontinuous modulation types using deliberately designed offset voltages to minimize dc-link voltage variation. Notably, setting the offset voltage to zero interestingly implements conventional virtual-vector PWM. The sum of the product of the duty ratios of the basis vectors and the phase currents was analyzed, and its relationship with the dc-link voltage fluctuation was mathematically rigorously examined. Through various simulations and prototype experiments, the steady-state operational characteristics of the proposed method have been validated, demonstrating lower average switching frequencies and superior total harmonic distortion performance compared to conventional method. The proposed method demonstrates overall superior performance in total harmonic distortion (THD) compared to the conventional carrier-overlapped PWM (COPWM) technique. At a power factor (pf) of 0.9, it provides comparable or slightly better performance, while at pf =0.3 and a modulation index (m) of 0.3, it exhibits significant improvements. Specifically, the proposed method reduces the output voltage THD to 86%-126% and the output current THD to 4.65%-5.45%, outperforming the COPWM, which recorded 121% and 7.35%, respectively. Additionally, proposed method reduces the average switching frequency by approximately 30% and the control operation time by about 22% compared to existing methods. The stability of the dc-link voltage equilibrium under transient conditions was also successfully verified.

In this paper, a three-phase diode-clamped four-level PWM inverter with offset voltage injection is proposed. The proposed inverter is based on multi-neighboring reference vector (discontinuous) pulse-width modulation (MNRV (D)PWM), where multiple adjacent reference vectors with different charging/discharging characteristics of the capacitors are selected depending on the location of the command voltage. These reference vectors are evenly utilized, and the duty ratio of the remaining reference vector as a degree of freedom is adjusted to satisfy the volt·time product. Additionally, the proposed MNRV (D)PWM can generate various (D)PWM forms by applying the offset voltage injection method. By extending the methodology applied to the four-level inverter, a general MNRV (D)PWM method applicable to general high-dimensional multilevel multiphase PWM inverters is also proposed. It is demonstrated that MNRV (D)PWM can be applied not only to dc/ac but also to dc/dc topologies. The ripple component of the dc-link voltage has been confirmed to be related to the three-phase summation of the product of the duty of the E voltage level vector and the phase current. Through various simulations and prototype experiments, the steady-state operating characteristics have been confirmed, demonstrating reduced average switching frequency and superior THD performance compared to conventional methods. Furthermore, proficient management of fluctuations in the dc-link voltage reference and sustained voltage equilibrium are exemplified.

In this paper, we propose a novel full-bridge (FB) diode-clamped four-level symmetric switching converter. Multi-neighboring reference vector discontinuous PWM (MNRV DPWM) for FB topology was implemented using a symmetric half-bridge (HB)-based control approach that incorporates an offset voltage addition method. A diode-clamped four-level symmetrical switching circuit with pulse-amplitude-modulation (PAM) was proposed and its working principle was explained in detail. Voltage gain, duty loss factor, and zero-voltage-switching (ZVS) condition were derived by analyzing the steady-state operating characteristics of the proposed converter. The required input and output capacitance values were also calculated explicitly. The voltages across the series-connected input DC-link capacitors were well balanced and the output voltage was controlled in a simple linear manner by PAM. The proposed method offers the advantage of reducing circulating current when compared to the existing phase-shift method, thanks to the inclusion of an additional power delivery period. The effectiveness of the proposed converter was verified through simulation and prototype experiments. The power conversion efficiency exceeded 91.44% at an output power ( $P_{O})$ of 250W or higher, with a peak efficiency of 95.23% achieved at $P_{O}=750\text{W}$ .

Bipolar hybrid ac/dc microgrid (MG) controls a DC and AC bus at the same time, supplies local loads with local resources, and offers multiple levels of dc voltages to resources and services. The applications are getting more popular in power systems. Due to its vital tasks in numerous applications, the interlinking converter (ILC) is an utmost crucial portion of the MG system. From this study, a 10‐switch converter is provided as an ILC for a hybrid MG, which gains from both two‐level (2L) and three‐level (3L) converters at the same time, and it can be used to a wider range of power levels. This work provides a space vector modulation (SVM) for a 10‐switch converter to maximize dc‐link voltage consumption and minimize total harmonic distortion (THD) compared with other modulation techniques. The behaviour of the suggested SVM is compared with that of sinusoidal PWM. The suggested SVM was evaluated using OPAL‐RT to show that it used DC bus voltage more reliably and produced significantly less THD than existing techniques. Furthermore, grid‐tied ILC's architecture is improved to reduce low‐order harmonics and used for dc‐link voltage balancing. A real‐time (RT) digital simulator (OP‐5700) was used to test the inverter control technique. In MG, this hardware‐in‐the‐loop simulation provides an excellent environment for designing and verifying system‐level control algorithms. Simulations were run in a MATLAB/Simulink environment and confirmed using an RT simulator to validate the feasibility of the suggested topology. [ABSTRACT FROM AUTHOR]

The effects of varying modulation indices on the current and voltage harmonics of an induction motor (IM) powered by a three-phase space vector pulse-width modulation (SVM) inverter are presented in this research. The effects were examined using simulation and an experimental setup. IMs can be governed by an SVM inverter drive or a phase-angle control drive for applications that require varying speeds. The analysis of THD content in this study used the modulation index (MI), whose modification affects the harmonic content, and voltage-oriented control (VOC) with SVM in three-phase pulse-width modulation (PWM) inverters with fixed switching frequencies. The control technique relies on two cascaded feedback loops, one controlling the grid current and the other regulating the dc-link voltage to maintain the required level of dc-bus voltage. The control strategy was developed to transform between stationary (α–β) and synchronously rotating (d–q) coordinate systems. To test the viability of the suggested control technique, a 1-hp/3-phase/415-V experimental prototype system built on the DSPACE DS1104 platform was created, and the outcomes were evaluated with sinusoidal pulse-width modulation (SPWM). [ABSTRACT FROM AUTHOR]

The Neutral Point Clamped (NPC) Multi-Level Inverters (MLI) have been ruling the power electronics industries for the past two decades. The Multi-Carrier Pulse Width Modulation (MCPWM) is common PWM techniques which are widely used in NPC-MLI applications. However, MCPWM is not having a good impact on the balancing of DC-link voltages, Common Mode Voltage (CMV) and limiting the Total Harmonics Distortion (THD). The Selective Harmonic Elimination (SHE) technique is introduced for reducing the THD, however all the switching angles should be maintained less than $\pi $ /2 to keep the eliminated harmonics at constant level which narrows down the modulation index range. Hence, in recent days Space Vector Modulation (SVM) technique is widely used in NPC-MLI, which gives better DC-link voltage balancing, self-neutral point balancing, near-zero CMV reduction, better-quality harmonics profile and switching loss minimization. Hence, it is a preferred solution for the majority of electrical conversion applications such as electric traction, high power industrial drives, renewable power generation, and grid-connected inverters, etc. The paper gives a comprehensive review of the SVM for NPC-MLI. First, this paper deliberates the state of art for two-level SVM and extends it to three-level (3L) SVM. Also compares the 3L SVM performance with other MCPWM techniques. Followed by the various modified MLI SVM techniques in terms of their implementations, DC-link capacitor balancing, and reduction of CMV. Further, the review of MLI SVM is widened to open-end winding Inverters and multiphase MLIs. The final part of this paper discussed the future trends and research directions on MLI SVM techniques and its applications.

Cascaded H-Bridge (CHB) converters have been widely employed in various applications, providing the advantages of modularity and multilevel voltage output. However, technically the CHB converters require isolated DC-link buses, which need to be regulated individually. In this context, a control scheme for the CHB converters features the voltage balancing algorithm. The voltage balancing control is typically performed by PI controller, where its control capability is limited by linear modulation region. In this work, the modulation based voltage balancing algorithm is proposed, which extends the balancing control capability and improves the dynamic performance. The proposed method is theoretically analyzed and validated through the simulation and experimental results.

This paper presents a novel concept of the DC-AC system with the input voltage boost ability, seven-level output voltage modulation, and the input AC current reduction at the double frequency of the output voltage. The system integrates the NPC full-bridge inverter which is composed of four-level legs and an active input voltage balancer (AIVB). The DC-link is composed of three capacitors connected in a series. The source of the energy is connected directly to the middle capacitor while the upper and lower capacitors of the DC-link are charged by the AIVB. The operation of the AIVB leads to balancing of the DC-link voltage and a three-fold boosting of the input voltage. The AIVB utilizes a novel switched-capacitor (SC) topology and can be designed as a low-volume quasi-magneticless converter with a simple open-loop control. One of the proposed methods of the control of the AIVB allows for a double frequency reduction in the input current. The application of the AIVB allows for the use of a seven-level NPC full-bridge (FB) inverter with a simple classic carrier-based PWM which is not applicable in the typical DC-link configurations. This paper presents the converter's concept, its operation, control methods, and the results of simulations and experiments. [ABSTRACT FROM AUTHOR]

A bipolar hybrid microgrid is a new topology which benefits from the advantages of both alternating current (AC) and direct current (DC) microgrids. Interlinking AC/DC converter is the key of this topology which has the following characteristics: being able to provide two equal pole voltages in DC side; complying with the standards of current quality at AC side; being able to control active and reactive power independently in AC side, and transmitting bidirectional power. In this paper, two categories of power converters including single-stage and two-stage converters are proposed for this topology. A new cost-effective control strategy is added to the control of general grid-connected converter for each interlinking converter, and the control of autonomous DC-link pole voltage for both candidates is achieved. Detailed simulations based on the designed control strategies are conducted to validate the function of control strategies under the operation conditions of different DC sides. The performances of two selected interlinking converters with balanced and unbalanced DC loads are analyzed. Suggested power quality of microgrid and total harmonic distortion (THD) analysis are demonstrated in grid-tied and islanded modes. Eventually, semiconductor power loss simulations based on a closed-loop thermal network simulation are conducted. Thereby, the mutual effects of power loss and initial junction temperature are investigated.

This paper proposed a grid connected solar Photovoltaic (PV) Systems with a new voltage balancing converter suitable for Neutral-Point-Clamped (NPC) Multilevel Inverter (MLI). The switched-capacitors used in the proposed converter is able to balance the DC link capacitor voltage effectively by using proper switching states. The proposed balancing converter can be extended to any higher levels and it can boost the DC input voltage to a higher voltage levels without using any magnetic components. This feature allows the converter to operate with the boosting capability of the input voltage to the desired output voltage while ensuring the self-balancing. In this paper the proposed converter is used for a grid connected solar PV system with NPC multilevel inverter, which is controlled using vector control scheme. The proposed grid connected solar PV system with associated controllers and maximum power point tracking (MPPT) is implemented in Matlab/SimPowerSystem and experimentally validated using dSPACE system and designed converters. The simulation and experimental results show that the proposed topology can effectively balance the DC link voltage, extract maximum power from PV module and inject power to the grid under varying solar irradiances with very good steady state and dynamic performances.

In this paper a DC-link voltage balancing strategy for multilevel Cascaded H-Bridge (CHB) converter is proposed. Presented solution bases on optimal choice of active vector durations in Space-Vector Pulse Width Modulation (SV-PWM). It makes it possible to DC-link voltages control and to properly generate the output voltage vector in the case of DC-link voltage unbalance. Results of simulation and experimental researches on proposed control strategy are presented in the paper

CHB is a suitable type of topology for synchronous rectifier application which has two or more independent DC loads. Focusing on the individual DC-link capacitor voltage balancing problems caused by asymmetric parameters of independent DC loads, this paper developed a new dual modulation signals based phase disposition pulse width modulation (PD-PWM) strategy using dynamic carrier bias allocation method. Its main idea is to allocate the bias of the carrier wave dynamically according to the balance situation of the system. Compared with the traditional modulation strategies, this method is more easily to be realized and has much stronger dynamic regulation ability. This modulation strategy is widely applicable to various types of CHB structures. A detailed analysis of the DC-link capacitor charge-discharge profile is performed, and an operation condition based dynamic bias allocation method is described using the cascaded H-bridge rectifier (CHBR) structure of five sub-modules as an example. A simulation model and an experiment platform are developed, and the feasibility and effectiveness of the modulation strategy are verified by simulation and experiment results.

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.

CHB is a suitable type of topology for synchronous rectifier application which has two or more independent DC loads. Focusing on the individual DC-link capacitor voltage balancing problems caused by asymmetric parameters of independent DC loads, this paper developed a new dual modulation signals based phase disposition pulse width modulation (PD-PWM) strategy using dynamic carrier bias allocation method. Its main idea is to allocate the bias of the carrier wave dynamically according to the balance situation of the system. Compared with the traditional modulation strategies, this method is more easily to be realized and has much stronger dynamic regulation ability. This modulation strategy is widely applicable to various types of CHB structures. A detailed analysis of the DC-link capacitor charge-discharge profile is performed, and an operation condition based dynamic bias allocation method is described using the cascaded H-bridge rectifier (CHBR) structure of five sub-modules as an example. A simulation model and an experiment platform are developed, and the feasibility and effectiveness of the modulation strategy are verified by simulation and experiment results. [ABSTRACT FROM AUTHOR]

This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications. [ABSTRACT FROM AUTHOR]