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This article addresses the shift of power that occurred in Ottoman Damascus as a result of the establishment of its electricity and tramway network that started operating in 1907. The company, which ought to have been public, in the ownership of Ottoman-Syrian investors, ended up being owned by a Belgian consortium. The central argument in the article is that the Damascene elite families rationally refrained from the risk of establishing the Electricity Company but paid the price of losing control over power and light in the city. An informal network of Ottoman officials and Belgian businessmen, led by the second secretary of Sultan Abdülhamid II, the Damascene İzzet Pasha, orchestrated the buyout. Therefore, Damascus's encounter with its first electric grid, which was naturally complex in the first place, was also subjected to the tensions of outsourcing a local-municipal power to an external network that the Central Ottoman Government imposed. This article is an outcome of research on the electrification of Damascus, based on the papers of the Ottoman Ministry of Public Works from the Ottoman Archive and the company's records from Belgium's National Archive, the Ottoman-Syrian press, and the British and American consulates' archives. [ABSTRACT FROM AUTHOR]

The article presents the discussion on Soviet citizen Mikhail Borisovich Gol'man penning one last report from Ankara. Topics include elaborating on Communist International smuggling material and people from Anatolia to Syria and Iraq; and Damascene origins and stints in pre-Comintern Ottoman socialism making ideally situated for the mission.

The renowned Syrian ʿālim Shaykh Muhammad Sa'id Ramadan Al-Buti was one of the world's leading scholarly representatives of Sunni Islam in contemporary times. The written debates that occurred between the Damascene ʿulamā', al-Buti, and the iconic Salafi scholar and ḥadīth scholar Muhammad Nasir al-Din al-Albani constitute one of the most important and comprehensive intra-Muslim debates in the twentieth century, having helped to define a clear schism between the neo-traditionalist position and its presumed opposite: Salafism. This article suggests that the rhetoric of anti-Salafism needs to be studied further to better understand contemporary currents in modern Islamic intellectual history. The adversarial rift that crystallised in the thriving Shāmī scholarly milieu of the 1980s and 90s informed the existence of a distinct neo-traditionalist school both in the West and many parts of the Muslim world for the latter part of twentieth century and to this day. At the intersection of political competition, textual methodology and competing visions of heresy and history, Islamic neo-traditionalism represents a key contestant in the battle for religious authority in contemporary Islam under the secular nation-state. Between championing a constructed concept of a 'tradition' for modern times and those who seek to return to a pristine 'true Islam', a deadlock is inevitable. [ABSTRACT FROM AUTHOR]

Thermal conductivity of copper and tungsten nanowires, copper damascene structures are modeled theoretically on the basis of Boltzmann transport equation. The size-dependent thermal conductivities of the nanowires are obtained by taking into account interface scattering, grain boundary scattering, and interface roughness effect. Expressions for the thermal conductivity of thin films including the above mechanisms are extended to the case of rectangular cross-sectional nanowires. The fractal model is also used to predict the contribution of interface roughness to the thermal conductivity of nanowires. It is shown that the interface roughness is important for the nanowires with lateral dimensions down to the sub-30 nm region. Calculated thermal conductivities are in good agreement with the experimental data for copper and tungsten nanowires. Furthermore, it is found that the titanium nitride barrier layer obviously leads to further thermal conductivity reduction in the copper damascene structures. [ABSTRACT FROM AUTHOR]

Electromigration (EM) reliability was investigated for Cu fine lines fabricated using a SiON trench filling process down to 60 nm in linewidth. EM was observed to be dominated by intrinsic failures due to void formation in the line trench. The lifetimes of 60 nm lines were longer than those of 125 nm lines with the standard damascene structure which can be attributed to a distinct via/metal-1 configuration with less process-induced defects at the via interface. The line scaling effect on EM reliability was investigated using three linewidths: 60, 110, and 185 nm. EM lifetimes were found to be similar for different linewidths, consistent with intrinsic failures caused by void formation in the line trench driven by interfacial mass transport. Statistical, multilinked EM test structures demonstrated a monomodal failure distribution for the fine lines, indicating suppression of processing-induced extrinsic defects although processing control on line dimension and geometry remained an issue. The activation energies were found to be around 0.80 eV for both fine lines and standard lines, indicating that interface diffusion dominates mass transport in Cu lines. [ABSTRACT FROM AUTHOR]

Surface electromigration rates on oxide-free surfaces of unpassivated damascene Cu interconnect segments have been determined through electromigration testing under vacuum. Electromigration-induced voids grew at the cathode end of the segments due to a flux divergence at refractory-metal-lined vias to the lead lines below the test segment. Copper diffusivity on a clean Cu surface was determined by measuring the size of the voids as a function of time and test temperature at a fixed current. An activation energy of 0.45±0.11 eV and a prefactor of 3.35×10-12 m2/s were found for the product of the effective charge z* and the surface diffusivity Ds. This result is shown to be consistent with void drift rates measured in passivated interconnects. [ABSTRACT FROM AUTHOR]

Narrow W lines with linewidths down to ~40 nm were manufactured by both damascene and subtractive processing. The dependence of the resistivity on the linewidth was studied for different deposition temperatures of the W layer. Generally, the resistivity decreases for decreasing deposition temperature of W. The resistivity increases with decreasing linewidth for both processes due to size effects. However, the W damascene lines show a much steeper increase of the resistivity than etched W lines. In the case of the etched lines the grain size is already fixed after deposition of the W and, therefore, the resistivity increase is caused by an increase of the surface scattering contribution solely. In the case of the damascene lines the line geometry restricts the grain size and, therefore, with decreasing linewidth both an increase of the grain boundary scattering and of the surface scattering contributes to the resistivity. The different behavior of the resistivities can be understood within a compact model describing the size effect. [ABSTRACT FROM AUTHOR]

Damascene Cu interconnects show significant differences in both their microstructural and stress behavior as compared to those of Al interconnects patterned using the etching process. Thermal stresses build up during the successive thermal cycles due to the differences in the coefficients of thermal expansion of the component materials. Other than these thermal stresses, growth stresses originating from grain growth develop in damascene Cu interconnects as well. In this study, the linewidth dependence of the stress in damascene Cu was examined experimentally, as well as by numerical simulation. The stresses of damascene Cu with widths ranging from 0.13 to 2 μm were measured using x-ray diffraction, and the measured hydrostatic stress was found to increase with increasing linewidth, in contrast to the typical behavior of Al interconnects. Microstructure analysis using transmission electron microscopy revealed that the grain sizes increased with increasing line dimensions. The increase in stress in the interconnect with increasing dimensions is attributed to the larger grain size, which induces higher growth stress in addition to the thermal stress. The contribution of the growth and thermal stresses of the damascene lines were quantified based on the grain size data utilizing finite element analysis. In this way, the linewidth dependence of the hydrostatic stress of damascene Cu was clearly explained. Finally, the effect of growth stress on the stress-related reliability is discussed. [ABSTRACT FROM AUTHOR]

Electromigration lifetime was studied on 0.23 μm wide Cu dual-damascene lines connected to underlying W lines with a TaN/Ta liner and SiN[sub x]/SiO[sub 2] insulator. The failure criteria used to study electromigration lifetime were based on the increase in test line resistance. Over 900 samples were tested to observe early electromigration Cu lifetime. Experimental results show that the lifetime distribution of samples tested using a failure criterion of 1% (3 Ω) resistance increase at the test temperature is best described by a trimodal function. However, the lifetime distribution of samples tested using a failure criterion of 50% is best described by a bimodal function. This difference in lifetime distribution is due to three types of observed deviant line resistance behaviors (plateau, fluctuating, and uphill) of certain samples which are caused by different types of void growth and a variation in liner stability. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

An in situ electromigration apparatus was used to study the kinetics of void growth in unpassivated, electropolated copper damascene lines. Voids were observed to grow by consuming grains in a stepwise fashion, either by grain thinning or by an edge displacement mechanism. Surface diffusion was found to be the primary diffusion path for void growth. In addition, grain boundaries provided a secondary path for copper diffusion in polycrystalline structures and nucleation sites for void growth in bamboo structures. Void growth rate was measured as a function of sample temperature and linewidth using a scanning electron microscope. An electromigration activation energy of 0.9±0.1 eV was determined for the copper voiding process. The effect of linewidth on void growth rate was also investigated and found to be negligible, consistent with a surface-diffusion dominated model for void growth. The in situ apparatus also made it possible to directly correlate changes in electrical resistance with physical changes taking place in the test structures. [ABSTRACT FROM AUTHOR]

Presents information on a study which analuzed the drift behavior of bamboo reactive ion etched and damascene Al(Cu). Experiment; Results and discussion; Conclusions.

Printing processes are increasingly used in the fabrication of organic field effect transistors (OFETs) owing to their merits of low cost, low processing temperature, vacuum-free nature, and compatibility with various substrates. Among various printing processes, transfer printing is preferable because of its high resolution and pattern fidelity. Here, we fabricate OFETs using directed assembled and transfer printed carbon nanotube (CNT) source/drain electrodes. The CNT electrodes are selectively assembled on a Damascene template using an electrophoretic directed assembly based inking process and then transferred onto a polyurethane film on a silicon substrate with a high pattern fidelity. Selective inking and direct transfer without sacrificial layers or intermediate transfer steps enable a high material efficiency and a low cost of our fabrication process. The fabricated OFETs with a spin-coated 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene semiconducting film show typical p-type behavior with an on/off ratio of approximately 105, implying great potential to use our method for practical OFET fabrication. [ABSTRACT FROM AUTHOR]

In this contribution highly sensitive and quantitative analytical methodologies based on femtosecond Laser Ablation IonizationMass Spectrometry (fs-LIMS) for the analysis of model systems and state-of-the-art Cu interconnects are reviewed and discussed. The method development introduces in a first stage a 1D chemical depth profiling approach on electrodeposited Cu films containing periodically confined organic layers. Optimization of measurement conditions on these test platforms enabled depth profiling investigations with vertical resolution at the nm level. In a second stage, a matrix-free laser desorption methodology was developed that allowed for preliminary molecular identification of the embedded organic contaminants beyond elementary composition. These studies provided specific fragmentation markers in the lower mass range, which support a previously proposed reaction mechanism responsible for successful leveling employing a new class of plating additives for Damascene processes. Further combined LIMS and Scanning Auger Microscopy (SAM) studies on through-silicon-vias (TSV) interconnects confirmed the embedment upon plating of the organic additives at the upper side-walls of the TSV channel in the boundary between the Cu seed layer and the electrodeposited Cu. [ABSTRACT FROM AUTHOR]

An overview of process and quality control issues faced in controlling copper damascene plating is provided. The challenges for effective management of a copper damascene plating process have evolved due to early limitations and problems which were discovered, and then as more demands resulted from Chemical Mechanical Planarization issues, yield and reliability concerns, reduction in critical feature size and the shift to 300 mm wafers as well as the adoption of dielectric films with low dielectric constants. The demands have been addressed by adherence to quality control methodology, improvements in plater design and operation, advancements in plating electrolytes, and by new metrology tools and methodology. The key measurement areas outlined here are bath concentrationmeasurement and control, film properties metrology, contamination issues, and defects. Particular attention is given to the use of electrochemical and optical methods with enhanced capabilities. This includes the use of chemometrics for electroanalytical bath concentration control and optical methods for film thickness, surface roughness, and film stress/wafer curvature measurements. [ABSTRACT FROM AUTHOR]

The effect of plating chemistry on standard damascene integration has been investigated to assess their effect on the interface quality of the final barrier/seed/fill integration. Dipping Co/TaN/SiO2 and Cu/TaN/SiO2 substrates wafers in acidic copper plating chemistry and ligand-based alkaline copper plating chemistry (aveni solution) shows that only the latter maintain the integrity of the substrate while the former degrades the seed (Co or Cu) and the barrier (TaN). We demonstrate that this degradation is extremely fast in the case of a cobalt seed thus only an alkaline ligand-based chemistry is compatible with a direct copper plating on cobalt seed approach. These results are critical because of the ever-going trend of decreasing semiconductors features size that requires the thinning down and removal of disposable metal layers while still maintaining the quality of the interfaces and the integrity of the whole integration. [ABSTRACT FROM AUTHOR]

A multi-level via or ‘supervia’ (SV) is considered as a scaling booster for the next technology nodes, as it may lower routing resistance and parasitic capacitance as compared to a conventional dual damascene (DD) via. In this paper, we present a three-level SV integration scheme at 16 nm half-pitch along with its 3-D RC extraction. 3-D interconnect geometries are modeled by means of process emulations, performed by using Synopsys' Sentaurus Process Explorer. The resistance of DD vias is also extracted for comparing with SV for various metal and barrier-liner (M-BL) combinations. The R extraction is done based on a resistivity model, calibrated to imec hardware and integrated into Synopsys' Raphael™ tool [1]. Simulations of SV structures with novel M-BL combinations show up to 60% resistance reduction for the investigated interconnect configurations with respect to the DD Cu-TaNCo reference ( R  = 105 Ω) at a total BL thickness of 3 nm. Furthermore, an approach to compare SV vs DD via capacitance is proposed, which suggests ~16% reduction in parasitic capacitance of SV schemes compared to DD schemes. [ABSTRACT FROM AUTHOR]

This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- \mu \textm line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 20~\mu \text{m} or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs. [ABSTRACT FROM PUBLISHER]

The heating surface of a coal-fired boiler is susceptible to high-temperature sulfur corrosion. To investigate and address this problem, a h-BN-based ceramic coating was prepared on the surface of a 20CrMn steel sheet using the slurry method. After sintering, the coating had a relatively dense surface with only a small number of microcracks. The coating and the substrate exhibited a metallic damascene structure and were well bonded. The high-temperature-corrosion behavior of the uncoated and ceramic-coated steel sheets in sulfur dioxide (SO 2 ), hydrogen sulfide (H 2 S), and sulfate environments was investigated. The results show that the coating could effectively prevent inward diffusion of sulfur, and it exhibited high-temperature-corrosion resistance. The high-temperature-corrosion resistance of the coated steel sheet was 8, 7, and 1.7 times that of the uncoated steel sheet in the SO 2 , H 2 S, and sulfate environments, respectively. After corrosion in the SO 2 and H 2 S atmospheres, potassium sulfate (K 2 SO 4 ) crystal grains were formed on the surface of the coating. However, because the coating was relatively dense, thus preventing S diffusion, the presence of K 2 SO 4 was not detected inside the coating. [ABSTRACT FROM AUTHOR]

In this work, we propose a damascene process to fabricate embedded gold micro- and nano-structures at the same time. We present a systematic study of the material removal rate (MRR) and the selectivity on both gold and silicon dioxide. The embedded microstructures are 2 μm wide and 60 nm deep, while the nanostructures widths vary from 70 nm to 500 nm for a 50 nm depth. Moreover, we highlight the contribution of the CMP in polishing the surfaces of gold films. Morphological characterizations are performed using mechanical profilometry, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). MRR and selectivity are evaluated as a function of time, applied pressure, platen rotation speed, and slurry flow. [ABSTRACT FROM AUTHOR]

Damascene process compatible Copper (Cu) surface passivation, ultra-smooth surface and enhanced Cu diffusion at the bonding interface are the key requirements for high quality, low temperature and low pressure Cu-Cu bonding for 3D integration applications. Manganin alloy deployed in this work as a passivation layer, performs dual role of protecting Cu surface from oxidation even at higher temperature (<300 °C) and provides surface smoothness of about 0.8 nm. Furthermore there is an inherent Cu 〈1 1 1〉 oriented plane formation with Manganin alloy passivated Cu surface. All the aforementioned factors are key enablers in enhancing diffusion of Cu across the bonding interface. This led to high quality Cu-Cu thermocompression bonding at sub 150 °C temperature and at a nominal contact force of 5 kN. Very low specific contact resistance of 1.45 × 10 −7 Ω-cm 2 and excellent bond strength of 186 MPa is clear evidence of the efficacy of optimized ultra-thin Manganin alloy as a passivation layer. [ABSTRACT FROM AUTHOR]

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step. [ABSTRACT FROM PUBLISHER]

Commercial tribunals (mehakim-i ticaret) were set up in the Ottoman Empire in the mid-nineteenth century in the framework of the Tanzimat reforms. Both in the capital and in leading provincial centres, these new institutions were geared to deal with all types of commercial litigation and especially with disputes involving non-Ottoman traders. This essay explores the first decades of operation of the commercial tribunal in Damascus: its origins and foundations, the interference of the foreign consular corps, and most prominently, the question of admissible proof. It investigates how oral witnessing and written evidence were handled in order to show that notwithstanding the adoption of the French Code de Commerce, the actual practice of the tribunal accommodated elements from diverse legal cultures. The proofs brought before the court both reflect the pluralist nature of Damascene trade and demonstrate the adaptability of Ottoman commercial jurisdiction in the reform period. [ABSTRACT FROM AUTHOR]

Five different parts of Rosa damascene Mill, twigs were treated with hormone solution (50 mg/L NAA + 100 mg/L IBA) and planted in base material. After 50 d of growth, the survival rate and rooting condition were investigated. The results showed that the survival rate from 5 different parts of cutting stem decreased from top to bottom (upper98.22%, middle and upper 95.12%, middle 91.10%, middle and lower 72.90%, lower 71.12%). The same results were also observed in the number, total length and fresh weight of secondary roots of cutting segments from different parts of twigs. [ABSTRACT FROM AUTHOR]

Alloy seedlayers for copper back-end of line interconnects have become common at technology groundrules of 45 nm and below, due to reliability requirements. The key requirement of the minority alloy component (e.g., Al or manganese, also referred to as the “dopant”) is that it segregates to the copper (Cu)/dielectric cap layer interface in order to promote adhesion between the Cu in the line and the dielectric capping layer. The segregation beneath the dielectric cap has a complex dependence on many process parameters and needs to be monitored across the wafer. In this paper, we present a contactless, in-line, fast, and reliable Kelvin probe technique for the sub-surface detection of alloy segregation in Cu interconnects for sub-22 nm technologies. [ABSTRACT FROM AUTHOR]

A successful bottom-up fill of single Damascene test features is achieved by using a two-component additive package consisting of bis-(sodium-sulfopropyl)-disulfide (SPS) and Imep polymers (polymerizates of imidazole and epichlorohydrin). In addition, a remarkable leveling effect is observed. Clearly, the Imep additive combines bottom-up fill capabilities with leveling characteristics in one single polymer component. These unique hybrid properties of the Imep are rationalized on the basis of an extended N-NDR (N-shaped negative differential resistance) being present in the linear-sweep voltammogram of the SPS/Imep additive system during Cu electrodeposition. [ABSTRACT FROM AUTHOR]

Incorporation of a small amount of a secondary metal element such as tin, indium or aluminum into copper interconnects structures has been shown to improve the device reliability and electromigration. In this study, the incorporation of tin during copper damascene plating was investigated at conditions that allow void-free filling. The study focused on the effects of the additive package used, the current density, and the feature size on the tin incorporation. The Sn concentration in Cu was found to increase with the non-metallic impurity levels. Because the plating chemistry and plating current have strong impacts on the incorporation of the non-metallic impurities, they were also found to change the Sn incorporation. For example, Cu films plated at a lower current density, which showed higher non-metallic impurity levels, were also found to incorporate more Sn, opposite to the expectation from the more negative reversible potential of Sn. In addition, the Sn incorporation is also higher in narrow lines as compared with overburden films which, correlate well to findings for non-metallic impurity levels. By combining a plating chemistry which results in high non-metallic impurity levels and a low current density, 60nm wide Cu lines with up to about 0.1% Sn were plated, a 10-fold increase from the overburden film. [ABSTRACT FROM AUTHOR]

Effect of alloy seed on electromigration (EM) and stress migration (SM) has been analyzed based on Cu-based, dual-damascene technologies. It is found that the thickness of aluminium (Al) seed layer has strong impact on metal resistance, EM lifetime and SM performance. Thicker Al seed layer can induce higher metal resistance, improve EM lifetime better and bring more apparent negative shift of resistance during SM. [ABSTRACT FROM AUTHOR]

This study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10 µm used for 40 nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063 µm. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40 nm or below technology. [ABSTRACT FROM AUTHOR]

We present an air-gapped microcoaxial transmission line fabricated on low resistivity silicon substrate (ρ = 10 Ω·cm). The transmission line is based on a damascene copper process and has demonstrated superior microwave properties of low attenuation (<0.02 dB/mm) and a low and constant effective permittivity (∼1.02) in the frequency range of 0.1-40 GHz. The fabrication process has a low thermal budget, and can be easily integrated with the advanced Cu back-end-of-line CMOS to fabricate low-loss and high quality factor microwave and millimeter wave passives for system-on-chip applications. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1462-1465, 2014 [ABSTRACT FROM AUTHOR]

Highlights: [•] Adhesion strength of the interface composed of a Cu grain and SiN in damascene interconnect was evaluated. [•] Evaluated strength distributed on the crystal orientation map with a wide range of scatter. [•] Crystal orientation of Cu grain played an important role to the local adhesion strength. [ABSTRACT FROM AUTHOR]

A novel Cu reflow seed process which utilizes physical vapor deposition (PVD) technology components has been demonstrated for nanoscale dual damascene interconnects. Prior to Cu electroplating, small features can be partially filled with Cu by this newly developed Cu reflow seed process. It is confirmed that both suitable seed coverage and appropriate reflow temperature are required for achieving ideal reflow property. Bias conditions during Cu PVD dominate seed coverage in features, and processes at moderate bias are demonstrated to provide optimum bottom and sidewall coverage, while limiting field coverage. Overall Cu fill performance was enhanced significantly and more than a 60% improvement in via-chain yield is obtained by Cu reflow seed compared to conventional seed. Furthermore, Cu lines with fewer voids and less impurities are fabricated by repeating this Cu reflow seed process several times to obtain complete feature fill, which results in lower leakage current between lines. This Cu reflow seed process is a promising candidate for improving Cu fill performance for nanoscale Cu/low-k interconnects of 32 nm critical dimension and beyond. [ABSTRACT FROM AUTHOR]

Common open-source suppressors for copper filling of damascene interconnects include polyethylene glycol (PEG), polypropylene glycol (PPG), or a copolymer structure of both. Differences in the structure of these suppressors generate variations in polarization strength, surface adsorption rate, and SPS displacement rate. These properties were measured by electrochemical transient analysis and coupled with the results of time-evolved partial fill plating experiments on 32 nm and 45 nm node features to determine the effect of electrochemical property variations on the gap-fill characteristics. The high polarization strength of PPG, along with its greater dependence on concentration was found to greatly increase the bottom-up growth rate during copper filling, while the improved resistance to accelerator displacement of PEG resulted in better sidewall protection. Both these gap-fill characteristics were evident when PEG and PPG were combined together as a homopolymer mixture or in copolymer structures, although the overall influence was dependent on the size and configuration of each component. These data sets provided a more fundamental understanding of PEG, PPG and their different configurations role in the metallization of damascene interconnects. The relative gap-fill performance can also be inferred to screen new suppressor candidates and reduce the quantity of plating experiments by comparison of the electrochemical properties. [ABSTRACT FROM AUTHOR]

The electrodeposited Cu film morphology on thin physical vapor deposited (PVD) Cu seed for various conditions and correlation with Cu fill of dual Damascene structures is discussed. Thinner PVD Cu seed on Ta yields isolated electrodeposited Cu particles, while smooth plated films are obtained for thicker seed. Changes in suppressor additive and virgin makeup solution (VMS) concentrations have a limited impact on the morphology of Cu electrodeposited on thin Cu seed. Increased seed to plate queue time appears to lead to coarser, more isolated deposited Cu particles. Changes in Cu fill performance of dual Damascene structures having a 28 nm critical dimension (CD) were consistent with blanket wafer results for seed to plate queue times, but less so for changes in suppressor and VMS. A chemical vapor deposited (CVD) Co liner appears to improve the effective thickness of PVD Cu seed and hence the electrodeposited Cu film morphology for conditions considered in this study. [ABSTRACT FROM AUTHOR]

Impurities incorporated into copper during electrochemical deposition have long been postulated to inhibit grain growth in narrow interconnects. In this article we examine an alternative possible origin for the microstructural differences observed between narrow and wide lines. Specifically, the iPVD Cu seed layers in wide (1 µm) and narrow (70 nm) lines differ significantly in microstructure and texture, as analyzed by transmission electron microscopy and electron diffraction. The seed in the wide lines has a polycrystalline microstructure similar to that seen in blanket films, with strong 111 texture in the field and sidewalls, and 112 texture at the bottom of the trench. Although the field between the 70 nm lines is also strongly 111-textured, the seed on the sidewalls and bottom of the trenches are largely untextured and, in fact, not entirely crystalline. This results in a higher energy, metastable microstructure which can contribute an additional driving force for the rapid nucleation and recrystallization of polycrystalline copper in the trenches before the overburden can transform and force the creation of bamboo grains in the lines. [ABSTRACT FROM AUTHOR]

The electroplating characteristics of polyvinylpyrrolidones (PVPs) have been studied by means of potential/time transients, secondary ion mass spectroscopy (SIMS depth profiling) and NMR methods. Our results identify the PVPs as a class of Cu plating additives whose mode of leveler action can be controlled (switched on/off) by the current density. At low current densities the PVPs show identical synergistic effects with chloride and similar antagonistic effects with SPS (bis-(sodium-sulfopropyl)-disulfide) as known from the PAGs (polyalkylene glycols). In particular the SPS loses its depolarizing capability at higher current densities. The dominance of non-specific interactions of the PVPs with the copper surface is identified as origin for the leveling capability of PVPs at these higher current densities. The transition from an antagonistic (no leveling) to a non-antagonistic (leveling) PVP/SPS interplay is demonstrated to be depending on the molecular weight of the PVPs. [ABSTRACT FROM AUTHOR]

Superconformal Au deposition is demonstrated in a Na3Au(SO3)2 based electrolyte that exhibits critical behavior with addition of the deposition-rate suppressing additive polyethyleneimine (PEI). The critical behavior results from s-shaped negative differential resistance that is stabilized by the resistive electrolyte as evident in hysteretic cyclic-voltammetry. Specifically, the hysteretic potential range indicates conditions under which two states can exist: one in which adsorbed PEI suppresses gold deposition and the other in which ongoing gold deposition continues to disrupt and bury arriving suppressor. The specimen history determines the state observed. "Extreme" bottom-up filling of Through Silicon Vias (TSVs) and superconformal filling of submicrometer Damascene trenches are demonstrated and explained in this context. [ABSTRACT FROM AUTHOR]

Superconformal Au deposition is demonstrated in a Na3Au(SO3)2 - Na2SO3 based electrolyte using underpotential deposited (upd) Pb to catalyze the reduction of Au(SO3)23-. Micromolar additions of Pb2+ to the electrolyte give rise to acceleration of the Au deposition rate as evidenced by hysteretic voltammetry and rising chronoamperometric transients that convolve the diffusion, adsorption kinetics and coverage isotherm of the upd Pb catalyst. The catalytic activity on the Au deposition reaction may be quenched, or reset, by stepping the potential to more positive values to deactivate or strip the Pb catalyst. Void-free Damascene trench superfilling at various fixed potentials and Pb2+ concentrations is demonstrated and shown to be congruent with the curvature enhanced accelerator model (CEAC) of superconformal growth. This includes enhanced deposition due to catalyst enrichment on concave surface segments at the bottom corners of the trenches, followed by rapid bottom-up growth and, for certain conditions, bump formation above the filled trenches. [ABSTRACT FROM AUTHOR]

Highlights: [•] CMP process of 12in. GST blank wafer and pattern wafer with 60nm width damascene trenches in the acidic slurry. [•] Successfully EPD technique of GST CMP process using optical methods. [•] It has a little difference of EPD curve between blank wafer and pattern wafer. The EPD curve of pattern curve can divide into four stages. [•] Average dishing of GST are less than 3.5nm and the wafer-to-wafer variation is less than 8.0%. [•] A reproducible result is obtained using EPD technique although large variation of RR. [Copyright &y& Elsevier]