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High dielectric ceramic thin films incorporated into microelectronic packaging will extend both the performance and functions of advanced microelectronic packaging. The low processing temperatures, excellent composition control and low capital manufacturing costs may make the sol-gel film preparation route a prime manufacturing method. For this technique to be a useful alternative to competing vacuum deposition methods, the interactions between the commonly employed packaging materials set and the Sol gel derived films must be understood. To integrate these films into applications the development of thin film stresses and resulting defects must be understood. In this study, we are examining the processing of sol-gel derived barium titanate thin films for use as integrated decoupling capacitors as our model system. Stress measurements are made by measuring curvature of thin film coated wafers as a function of temperature and time. The films exhibit both plastic and elastic behavior at different processing stages. These films are microscopically examined to observe the formation of microstructure including cracking and pinholes. By tailoring the thermal process to the viscoelastic film behavior high quality films may be produced.

Ceramic formulations set in an organic binder are currently being cast in thin paper-like sheets. These sheets may be punched, screened with metal pastes, and laminated to form a composite of metal and ceramic particles held together by an organic medium. By slowly burning off the organic binder and then sintering the ceramic and metal together, a substrate with many layers of interconnecting wiring may be obtained. The coincident sintering of the ceramic and metal phases presents compatibility constraints. Temperature considerations with respect to shrinkage and coefficient of expansion match between the ceramic and metal phases as well as solid/solid and solid/ambient interactions are important constraints in the fabrication of these composites. High conductivity metals (e.g., Ag, Cu) are generally not available for co-firing because sintering temperatures of important ceramic formulations are higher than the melting points of these metals. This constraint has been minimized through the use of capillary infiltration of molten metals into the ceramic structure. Consequently, it is now possible for multilayer ceramic structures to provide the interconnection wiring densities and conductivities necessary to respond to the needs of greater circuit densities of integrated circuit chips. Material selections are reviewed on the basis of electrical properties, ambient interactions, stresses due to sintering shrinkage, and thermal coefficient of expansion. Certain problems, tradeoffs, and procedures used in the fabrication of a multilayer substrate with Cu-filtrated lines are discussed.