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Solder joints can experience fatigue cracking at the interface between the solder and substrate during thermal cycling due to the difference in thermal expansion between joined components. In order to strengthen the interfacial region and prevent cracking, two Cu pad surface treatments were studied on Sn-3Ag-0.5Cu solder, and on matte Sn plate and Ni plate coatings. The resulting intermetallic microstructures were characterized using scanning electron microscopy and energy-dispersive spectroscopy. Mechanical testing was performed using nano-indentation on the solder joints. The matte Sn plate on Cu sample formed an uneven distribution of Ag3Sn particles and a planar Cu6Sn5 interfacial intermetallic. The Ni-plated sample formed a needle-like Ni-rich interfacial intermetallic and uniform dispersion of Ag3Sn particles. The rough intermetallic compound (IMC)/solder interface and even IMC particle distribution cause the Ni-plated sample to experience reduced damage under board-level thermomechanical cycling because the interfacial structure reduces the Sn matrix recrystallization that contributes to fatigue cracking. In contrast, the matte Sn-plated sample exhibited an Ag3Sn particle-free zone adjacent to a planar Cu6Sn5 IMC layer which allows for rapid Sn recrystallization and fatigue crack propagation.

High strain-rate drop impact tests were performed for land grid array (LGA) packages with (electroless nickel immersion gold) ENIG metallization and lead-free solder interconnects. Sn-4Ag-0.5Cu (in wt%, SAC405), Sn-3.5Ag (in wt%), and Sn-0.7Cu (in wt%) were used for pretinning the LGA pads. SAC 405 alloy was used for the LGA-to-board mounting. Drop test results showed two distinct trends. Samples pretinned with Sn-4Ag-0.5Cu and Sn-3.5Ag showed poor drop performance while those pretinned with Sn-0.7Cu (in wt%) or without pretinning showed excellent drop performance. The dierence in behavior is related to the initial intermetallic morphology and structure. The needle shape Ni3Sn4-based intermetallics were observed for the first two cases. This led to poor adhesion between solder and NiP metallization. The samples with Sn-0.7Cu pretinning and no pretinning showed a continuous intermetallic morphology. In this case, sucient Cu improved the solder wetting and formed a continuous intermetallic morphology, leading to better drop performance. A sucient amount of Cu makes the better wetting, forming (Cu,Ni)

Consumer electronic applications are the primary target of the Pb-free initiative and package assembly and performance is affected by the move from eutectic Sn-Pb to Pb-free solder alloys. This paper outlines the key issues and mitigation possibilities for package assembly using Pb-free solders: High temperature reflow, Interfacial reactions, and Reliability. At the high temperatures required to reflow Pb-free alloys, moisture absorbed into the package can result in delamination and failure. The reaction of the Pb-free solder with Ni and Cu metallizations results in interfacial intermetallics that are not significantly thicker than with Sn-Pb but provide a path for fracture under mechanical loading due to the increased strength of the Pb-free alloys. The reliability issues discussed include thermomechanical fatigue, mechanical shock, electromigration and whiskering. The Pb-free alloys tend to improve thermomechanical fatigue and electromigration performance but are detrimental to mechanical shock and whiskering. Design trade-offs must be made to successfully implement Pb-free alloys into consumer applications.

IntroductionThe trend for microelectronic devices has historically been, and will continue to be, toward a smaller feature size, faster speeds, more complexity, higher power, and lower cost. The driving force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunications, rf applications are beginning to drive many areas of microelectronics that traditionally were led by developments in microprocessors. An increasingly dominant factor in rf microelectronics is electronic packaging, and the materials needed to create the package, because the package materials strongly affect the performance of the electronics. Many challenges remain for the packaging of microprocessors as well. These challenges include increased speed, the number of input/output interconnects, decreased pitch, and decreased cost. This article highlights the key issues facing the packaging of high-performance digital and rf electronics.

Intermetallic compound (IMC) growth during solid-state aging at 125, 150, and 170 °C up to 1500 h for four solder alloys (eutectic SnPb, Sn–3.5Ag, Sn–3.8Ag–0.7Cu, and Sn–0.7Cu) on Cu under bump metallization was investigated. The samples were reflowed before aging. During the reflow, the solders were in the molten state and the formation of the IMC Cu6Sn5 in the cases of eutectic SnPb and Sn–3.5Ag had a round scallop-type morphology, but in Sn–0.7Cu and Sn–3.8Ag–0.7Cu the scallops of Cu6Sn5 were faceted. In solid-state aging, all these scallops changed to a layered-type morphology. In addition to the layered Cu6Sn5, the IMC Cu3Sn also grew as a layer and was as thick as the Cu6Sn5. The activation energy of intermetallic growth in solid-state aging is 0.94 eV for eutectic SnPb and about 1.05 eV for the Pb-free solders. The rate of intermetallic growth in solid-state aging is about 4 orders of magnitude slower than that during reflow. Ternary phase diagrams of Sn–Pb–Cu and Sn–Ag–Cu are used to discuss the reactions. These diagrams predict the first phase of IMC formation in the wetting reaction and the other phases formed in solid-state aging. Yet, the morphological change and the large difference in growth rates between the wetting reaction and solid-state aging cannot be predicted.

A variety of lead-free solder alloys were studied for use as flip-chip interconnects including Sn-3.5Ag, Sn-0.7Cu, Sn-3.8Ag-0.7Cu, and eutectic Sn-37Pb as a baseline. The reaction behavior and reliability of these solders were determined in a flip-chip configuration using a variety of under-bump metallurgies (TiW/Cu, electrolytic nickel, and electroless Ni-P/Au). The solder micro-structure and intermetallic reaction products and kinetics were determined. The Sn-0.7Cu solder has a large grain structure and the Sn-3.5Ag and Sn-3.8Ag-0.7Cu have a fine lamellar two-phase structure of tin and Ag3Sn. The intermetallic compounds were similar for all the lead-free alloys. On Ni, Ni3Sn4 formed and on copper, Cu6Sn5Cu3Sn formed. During reflow, the intermetallic growth rate was faster for the lead-free alloys, compared to eutectic tin-lead. In solidstate aging, however, the interfacial intermetallic compounds grew faster with the tinlead solder than for the lead-free alloys. The reliability tests performed included shear strength and thermomechanical fatigue. The lower strength Sn-0.7Cu alloy also had the best thermomechanical fatigue behavior. Failures occurred near the solder/intermetallic interface for all the alloys except Sn-0.7Cu, which deformed by grain sliding and failed in the center of the joint. Based on this study, the optimal solder alloy for flip-chip applications is identified as eutectic Sn-0.7Cu.

The reaction kinetics of eutectic SnPb solder on Cu were studied and compared in the liquid state at 200 to 240 °C and in the solid state aged at 125–170 °C. The ternary phase diagrams of SnPbCu, the morphology of intermetallic compound (IMC), and the kinetics of growth of the intermetallics were used in the comparison. The temperature difference between these two reactions is only 30 °C, but the kinetics of reaction, as well as the morphology of IMC formation, are very different. The kinetics in the wetting reaction is four orders of magnitude faster than that in solid state aging. The Cu6Sn5 intermetallic morphology in solid state aging is a layer type, but it has a scallop-type morphology in the wetting reaction. The morphology strongly affects the kinetics. While the kinetic difference can be attributed to the difference in atomic diffusivity between the liquid state and the solid state, it is the morphology that determines the kinetic path in these reactions. We conclude that a fast rate of reaction,...

The electromigration of eutectic SnPb solder interconnects between a Si chip and a FR4 substrate was studied at 120 °C for up to 324 h with current stressing of 104 amp/cm2. Hillocks were observed at the anode and voids at the cathode. The dominant diffusing species was found to be Pb, confirmed by its accumulation at the anode. Diffusion markers were used to measure the electromigration flux and calculate the effective charge of atomic diffusion in the solder. Extensive microstructural evolution was also observed in the two-phase solder alloy that occurred by a ripening process.

A variety of Pb-free solder alloys have been proposed for use as interconnects for electronic packaging including Sn−Ag, Sn−Cu, Sn−Ag−Cu, Sn−Ag−Bi, and Sn−Sb, among others. This paper presents a review of the behavior of promising Pb-free solder alloys as related to their microstructure. Recommendations of optimal alloy composition as a function of performance requirements are given. For surface mount applications, eutectic Sn−Ag−Cu is recommended as the optimal alloy. For flip chip interconnects, the eutectic Sn-Cu alloy has the best performance. The materials and process trends of Pb-free packaging are summarized with optimal conditions identified.

We examined the interfacial morphology and shear deformation of flip chip solder joints on an organic substrate (chip-on-board). The large differences in the coefficients of thermal expansion between the board and the chip resulted in bending of the 1-cm2 chip with a curvature of 57 ± 12 cm. The corner bump pads on the chip registered a relative misalignment of 10 μm with respect to those on the board, resulting in shear deformation of the solder joints. The mechanical properties of these solder joints were tested on samples made by sandwiching two Si chips with electroless Ni(P) as the under-bump metallization and 25 solder interconnects. Joints were sheared to failure. Fracture was found to occur along the solder/Ni3Sn4 interface. In addition, cracking and peeling damages of the SiO2 dielectric layer were observed in the layer around the solder balls, indicating that damage to the dielectric layer may have occurred prior to the fracture of the solder joints due to a large normal stress. The failure behavior of the solder joints is characterized by an approximate stress analysis.

The wetting reaction between molten eutectic SnPb solder and a sputtered trilayer Cu/Ni(V)/Al thin film metallization was studied using cross-sectional transmission electron microscopy and scanning electron microscopy. Reaction temperatures were from 200 to 240 °C and reaction times ranged from 1 to 40 min. The initial reaction products were Cu6Sn5 and Cu3Sn. The latter transforms to the former after an annealing greater than 1 min at 220 °C. The Cu6Sn5 grains adhere well to the Ni(V) surface and no spalling of them was observed, even after 40 min at 220 °C. This surprising result indicates that the Cu/Ni(V)/Al or Cu6Sn5/Ni(V)/Al is a stable thin film metallization for low temperature eutectic SnPb solder direct chip attachment to organic substrates. Additionally, Kirkendall voids accompanied Cu3Sn formation, yet the voids disappear when the Cu3Sn transforms to Cu6Sn5.

Thermal mechanical fatigue (TMF) is an important damage mechanism for solder joints exposed to cyclic temperature environments. Predicting the service reliability of solder joints exposed to such conditions requires two knowledge bases: first, the extent of fatigue damage incurred by the solder microstructure leading up to fatigue crack initiation, must be quantified in both time and space domains. Secondly, fatigue crack initiation and growth must be predicted since this metric determines, explicitly, the loss of solder joint functionality as it pertains to its mechanical fastening as well as electrical continuity roles. This paper will describe recent progress in a research effort to establish a microstructurally-based, constitutive model that predicts TMF deformation to 63Sn-37Pb solder in electronic solder joints up to the crack initiation step. The model is implemented using a finite element setting; therefore, the effects of both global and local thermal expansion mismatch conditions in the joint that would arise from temperature cycling.

In interfacial reactions, a short-circuit diffusion along grain boundaries or interfaces can be accompanied by intermetallic compound formation. The compound penetrates the grain boundaries or the interfaces. This is a generic reliability issue for layered thin film structures because it causes a decrease in adhesion strength of the thin films. We have modified Fisher’s grain boundary diffusion model to include this reactive kinetic process, and an analytical solution was obtained. A t1/4 dependence of penetration is found, the same as Fisher’s model. The important kinetic parameters in the solutions are a diffusion coefficient along the short-circuit path, an intrinsic interdiffusion coefficient in the compound, and a partition coefficient. A comparison between the calculated and measured data from the lateral penetration of eutectic SnPb solder along the interface between electroless Ni and oxysilicon nitride dielectric, accompanied by Ni3Sn4 compound formation, is given.

Solder reaction-assisted crystallization of electroless Ni–P under bump metallization in the Si/SiO2/Al/Ni–P/63Sn–37Pb multilayer structure was analyzed using transmission electron microscopy, scanning electron microscopy, energy dispersive x-ray, and electron probe microanalyzer. The electroless Ni–P had an amorphous structure and a composition of Ni85P15 in the as-plated condition. Upon reflow, the electroless Ni–P transformed to Ni3Sn4 and Ni3P. The crystallization of electroless Ni–P to Ni3P was induced by the depletion of Ni from electroless Ni–P to form Ni3Sn4. The interface between electroless Ni–P and Ni3P layer was planar. From the Ni3P thickness-time relationship, the kinetics of crystallization was found to be diffusion controlled. Conservation of P occurs between electroless Ni–P and Ni3P, meaning that little or no P diffuses into the molten solder. Combining the growth rates of Ni3Sn4 and Ni3P, the consumption rate of electroless Ni–P was determined. Based upon microstructural and diffusion r...

The compressive creep and stress-strain behavior of the near-eutectic 60Sn-40Pb solder alloy has been investigated over the temperature range of −55 °C to 125 °C. The total primary creep strain is a strong function of stress and temperature: at lower temperatures and high applied stresses (i.e., near the power-law breakdown regime), it is quite large, while it is much smaller at higher temperatures and lower applied stresses. The compressive minimum creep rate as a function of stress and temperature is fit well by the Garofalo sinh equation. A discussion of the effective stress exponent, n eff, in the context of the Garofalo sinh equation is presented to understand trends in the creep data. The values of n eff, for the applied stress levels studied, are found to range from 3.09 to 5.00 at 125 °C, while they have a range of 10.75 to 15.79 at −55 °C. These trends are consistent with the interpretation of climb-dominated creep at higher temperatures and plasticity-dominated power law breakdown behavior at the lower temperatures. The microstructural observations suggest that, at elevated temperatures, deformation occurs by relative displacement of eutectic colonies in the solder microstructure accompanied by extensive grain coarsening in the colony boundaries. At lower temperatures (

The important issues in advanced area-array electronic packaging for semiconductor devices are materials driven. Some of the processing-driven materials issues include the effect of introducing a silicon device interface with copper pads and a low-κ dielectric, the effect of decreasing pitch and feature size on the package interconnects, the development and implementation of organic substrates, and advanced underfills for fine-pitch flip-chip applications. From a materials reliability aspect, important materials issues include enhanced solder interconnect reliability, α-particle-induced soft errors, and the introduction of lead-free solder alloys.

The most commonly used solder for electrical interconnects in electronic packages is the near eutectic 60Sn‐40Pb alloy. This alloy has a number of processing advantages(suitable melting point of 183°C and good wetting behaviour). However, under conditions of cyclic strain and temperature (thermomechanical fatigue) the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes the prediction of solder joint lifetime complex. A finite element simulation methodology to predict solder joint mechanical behaviour, that includes microstructural evolution, has been developed. The mechanical constitutive behaviour was incorporated into the time‐dependent internal state variable viscoplastic model through experimental creep tests. The microstructural evolution is incorporated through a series of mathematical relations that describe mass flow in a temperature/strain environment. The model has been found to simulate observed thermomechanical fatigue behaviour in solder joints.

A variety of new materials are needed for solder interconnects in electronic packages for high- and low-temperature applications. This article compares the mechanical behavior of low-temperature materials (Sn-40In-20Pb, Sn-58Bi, and a silver-loaded conductive adhesive) and high-melting-temperature solders (Sn-3.5Ag, Sn-3.4Ag-4.8Bi, and Sn-4.7 Ag-1.7Cu) to near-eutectic Sn-40Pb solder. The results indicate that there are promising materials alternatives to the traditional Sn-Pb solders in electronic interconnect applications.

The presence of an intermetallic is often an indication of good wetting in a solder joint. However, excessive intermetallic growth and the brittleness of the intermetallic layer may be detrimental to joint reliability. This study examined the growth and mechanical behavior of interfacial intermetallics between copper and six solder alloys commonly used in electronics assembly. The solder alloys tested were 60Sn-40Pb, 63Sn-37Pb, 95Sn-5Sb, 96.5Sn-3.5Ag, 50Pb-50In, 50Sn-50In, and 40In-40Sn-20Pb. The 50Sn-50In and 40In-40Sn-20Pb exhibited faster solid state growth of the intermetallic layer at 100 °C as compared to the near-eutectic Sn-Pb control solder. The 50In-50Pb had a slower growth rate, relative to 63Sn-37Pb, at the aging temperature of 170 °C due to slower reaction rate kinetics of indium with copper. The 96.5Sn-3.5Ag and 95Sn-5Sb had similar intermetallic growth rates at 170 °C and 205 °C, and the aging was comparable to that of the 63Sn-37Pb alloy. The 95Sn-5Sb solder/copper intermetallic had a faster growth rate of the Cu3Sn layer than was observed in the Sn-Ag or Sn-Pb alloys. Modified fracture toughness and low load indentation tests were used to characterize the mechanical behavior of the intermetallics. The intermetallics were harder than both the base metal and the solder alloy. The fracture behavior of the joints in tension was dependent upon the strength of the solder alloy. Solders with low strengths failed in the solder by plastic deformation. The failure of solders with higher strengths was dependent upon intermetallic thickness. When the intermetallic was thin, fracture occurred in the solder or at the solder/ intermetallic interface. As the interfacial intermetallic thickened, the fracture path moved into the intermetallic layer.

In early electronic technologies, circuit components were attached to circuit boards by mechanical means. The electrical leads were either twisted together or mechanically interlocked to a board prior to soldering. The possibility of an unreliable solder joint causing any kind of circuit failure was remote. Interconnections were made intrinsic to the board by applying solder to increase electrical and thermal conductance. Technological advances and the need for high-density electronics have since eliminated the luxury of mechanical interlocks. Soldering in advanced applications, like surface mount technology (SMT), provides electrical, thermal, and mechanical interconnections between the board and its electrical components. In SMT, solder joints are the only mechanical features on the board and must hold components in place in a wide range of environments. The solder joints themselves are decreasing in size as increased chip functionality and clock frequencies become available. The failure of a single solder joint can render a device, or an entire electrical system, inoperable. Therefore, as insignificant and innocuous as they may seem, solder joints have become a critical aspect of electronic circuit reliability.

The use of soft solders, particularly those containing lead, dates back nearly 5,000 years. Solders similar to the materials used to seal the aqueducts of ancient Rome are now an important building block in the manufacture of high-speed computer assemblies. This history attests to the technological versatility of soft solders and, in particular, the solder alloys that contain lead. However, the health effects of prolonged exposure to lead have also been documented; measures to limit human exposure—at the work place and indirectly through the environment—are being considered. The successful introduction of lead-free solders into future electronic products will rely heavily upon their solderability, which can be evaluated by test procedures such as the meniscometer/wetting balance technique and the capillary flow test.

We present the results of a metallurgical study of a 35Pd-30Ag-14Cu-10Au10Pt-1Zn (wt. %) alloy soldered with 60Sn-40Pb for glass-to-metal sealing applications. Mechanical tests were performed on the Pd-Ag-Cu-Au-Pt-Zn alloy and showed that it retains ductility, with an increase in strength, after heat treatments that simulate the glass-to-metal sealing temperature profile. Wetting characteristics of the alloy with 60Sn-40Pb solder were found to be adequate for pin joining applications. The formation and growth of the interfacial interme-tallic between 60Sn-40Pb and the Pd-Ag-Cu-Au-Pt-Zn alloy were characterized. The matrix of the intermetallic layer consists of PdSn4 with platinum and gold substituting for the palladium in the crystal structure. Also present were precipitates of Cu3Sn and Ag3Sn. Nano-indentation hardness tests showed that the intermetallic layer has mechanical properties similar to the base metal while retaining good ductility. The intermetallic was also found to have good wettability under solder reflow conditions. We conclude from these tests that the Pd-Ag-Cu-Au-Pt-Zn alloy is a suitable option as a pin material for glass-to-metal sealing applications.

The corrosion behavior of sputter-deposited Al, Al-Cu, and Al-Si alloy thin films in dilute hydrofluoric (HF) acid solution was investigated. These materials maintain a thin aluminum oxide film in dilute HF solutions and, consequently, are susceptible to localized corrosion. Pit densities increase for the alloys with Cu and, to a lesser extent, Si additions. Open circuit potentials (OCP) are more positive for such alloys relative to the OCP of pure Al. Metastable pits in Al-Cu alloys are formed in Cu-depleted zones at grain boundaries which are galvanically coupled to adjacent θ-Al2Cu precipitates. Metastable pits in Al-Si alloys are formed in the Al matrix which is galvanically coupled to adjacent elemental Si nodules. θ-Al2Cu has different electrochemical characteristics than Al, even though both maintain a thin Al oxide in dilute HF solutions. θ-Al2Cu has a more positive OCP than pure Al and facilitates cathodic reactions at enhanced rates relative to pure Al. Hence, its presence raises the potential of the adjacent pure Al grain boundary to potentials which increase the probability of metastable pitting. Evidence is also presented which suggests that metastable pit growth may be cathode limited. A new hypothesis describing one mechanism by which θ-Al2Cu supports cathodic electron transfer re-actions is discussed.

The grain size and grain growth kinetics in sputter deposited Al-2% Cu films on silicon substrates were determined by TEM for various film thicknesses and anneal times, temperatures and methods. Grain sizes were found to be typically lognormally distributed. The as- deposited grain size (d{sub o}) dependence on film thickness (TH) was found to be d{sub o} = C TH{sup {1/2}}, due to competitive grain growth during film formation. Annealed grain size (d) after Rapid Thermal Annealing (RTA) for time (t) at temperature (T) is described by the general equation d {minus} do = C TH{sup 0.7} {l brace}t exp ({minus}{Delta}E{sub a}/kT){r brace}{sup 1/8}, where {Delta}E{sub a} = 0.85 ev for 0.4 {mu}m films and {Delta}E{sub a} = 1.1 ev for 0.8 {mu}m films. Grain growth is largely saturated for these anneals. Grain growth is shown to be more extensive during RTA anneals than furnace annealing and more extensive in 0.4 {mu}m films than 0.8 {mu}m films for equivalent RTA cycles. The results are discussed in terms of models, simulations and previous results of grain growth in thin metal films. 21 refs., 4 figs.

The precipitation, dissolution, and reprecipitation processes of Al2Cu (θ phase) in Al-2 wt pct Cu thin films were studied. The films were characterized in the as-deposited condition, after annealing at 425 °C for 35 minutes, and after rapid thermal annealing (RTA) at 345 °C, 405 °C, and 472 °C. In the as-deposited samples, the precipitates had a fine even distribution throughout the thin film both at aluminum grain boundaries and within the aluminum grains. Annealing below the solvus temperature caused the grain boundary precipitates to grow and precipitates within the center of aluminum grains to diminish. Annealing above 425 °C caused the θ-phase precipitates to dissolve. Upon cooldown, the θ phase nucleated at aluminum grain boundaries and triple points in the form of plates.In situ heating and cooling experiments documented this process in real time. Analytical microscopy revealed that there is a depletion of copper at the aluminum grain boundaries in regions free of precipitates. The θ-phase precipitates nucleated and grew at the grain boundariesvia a collector plate mechanism and drew copper from the areas adjacent to the aluminum grain boundaries.

Thermomechanical fatigue tests were performed on two near-eutectic Sn-Pb solder alloys, 60 Sn-40 Pb and 62 Sn-36 Pb-2 Ag, to examine the effect silver additions have on solder joints. The cyclic load was found to have consistent trends between the two silver alloys (for given amounts of total strain and strain rates). It was found that a decreasing strain rate increased the life of both alloys equally in thermomechanical fatigue. At slower strain rates, the dislocation substructure recovers faster than it work-hardens, which tends to minimize subsequent recrystallization and heterogeneous coarsening of the solder joint. The microstructure of 62 Sn-36 Pb-2 Ag contained large whisker-like Ag/sub 3/Sn precipitates that nucleate and grow out from the Cu/sub 6/Sn/sub 5/ interfacial intermetallics. At this size, the Ag/sub 3/Sn precipitates have little effect on the deformation behavior of the solder. The intermetallics are not detrimental in that they do not prematurely crack, nor are they beneficial because they are too large to stabilize the microstructure. It does not appear, from a microstructural viewpoint, that adding silver to near-eutectic Sn-Pb has any significant effect on improving the thermomechanical fatigue behavior. >

A variety of Pb-free solders and under bump metallurgies (Cu, Ni, NiP) were investigated for flip chip packaging applications. The result shows that Sn-0.7Cu exhibits the most desirable mechanical properties (shear, tensile, aging, etc.) during deformation under a variety of stress conditions and has the most favorable failure mechanism under both mechanical and thermomechanical stress testing regardless of UBM type. The eutectic Sn-0.7Cu failed through bulk solder while the eutectic Sn-37Pb, Sn-3.5Ag and Sn-3.8Ag-0.7Cu failed at the solder and UBM interface, involving their respective intermetallic compounds. Cu UBM is more favorable for better reliability than NiP UBM from both interface IMC morphology and electromigration points of view. The current carrying capability for all alloys had no failures when stressed up to 2,338 hours at 2.6/spl times/10/sup 4/ A/cm/sup 2/ and 170/spl deg/C. However, when stressed at 5.1/spl times/10/sup 4/ A/cm/sup 2/, there is a significant migration of Pb toward the anode, creating a multiple layered Pb-rich and Sn-rich microstructure. An observation of excessive Ni migration away from the NiP UBM towards the anode after only 30 hours of current stressing at 5.1/spl times/10/sup 4/ A/cm/sup 2/ and 150/spl deg/C raised the reliability concern for solders with NiP UBM, especially for high power applications. The Sn-0.7Cu/Cu UBM and Sn0.7Cu/Ni UBM exhibit greater than 5,300 cycles of thermal fatigue characteristic life under -55/spl deg/C 1+150/spl deg/C and -40/spl deg/C /+125/spl deg/C air-to-air thermal cycling conditions, respectively.

Solder reaction-assisted crystallization of electroless Ni-P under bump metallization in the Si/SiO/sub 2//Al/Ni-P/63Sn-37Pb multilayer structure was analyzed using transmission electron microscopy, scanning electron microscopy, energy dispersive X-ray, and electron probe microanalysis. The electroless Ni-P had an amorphous structure and a composition of Ni/sub 85/P/sub 15/ in the as-plated condition. Upon reflow, the electroless Ni-P transformed to Ni/sub 3/Sn/sub 4/ and Ni/sub 3/P. The crystallization of electroless Ni-P to Ni/sub 3/P was induced by Ni depletion from electroless Ni-P to form Ni/sub 3/Sn/sub 4/. The crystallization kinetics were found to be diffusion-controlled.

A comprehensive method for testing solder joints under conditions of thermomechanical fatigue is presented. The method involves simultaneous imposition of temperature cycles and strain on discrete solder joints in a shear orientation. The stress, microstructure, and number of cycles to failure were monitored. Cycles to failure were determined by a continuous electrical detection method. 60Sn-40Pb and 40Sn-40In-20Pb solder joints were tested using the proposed method at 20% shear strain. The 60Sn-40Pb alloy has a shorter fatigue lifetime than 40Sn-40In-20Pb. This is attributed to heterogeneous coarsening strain in a small area of the 60Sn-40Pb microstructure. In contrast, the 40Sn-40In-20Pb microstructure becomes refined. The heterogeneous coarsening also results in cyclic softening in 60Sn-Pb, which was not observed in 40Sn-40In-20Pb. Failures initiated within the coarsened band in 60Sn-40Pb at Sn-Sn grain boundaries or phase boundaries. In contrast, failures initiated at the surface of 40Sn-40In-20Pb joints and propagated through both phases of the microstructure. >

The key conclusion out of the Solder Mechanics Workshop is that, overall, the technical and scientific community does not know as much quantitatively about solder behavior as we had hoped. The good news, however, is that the microelectronics user community, which is largely served by solder activities, has come to terms with the current environment through active participation in the workshop. The air has been cleared. As a technical community, we have a better idea of what our priorities for continued research are. A much more detailed overview of the workshop will be available shortly in monograph form. Individual chapters will be written by authors present at the workshop and will emphasize background material (e.g., literature critiques) and detail the technical consensus on critical issues central to the workshop. The book will be available through TMS and will be the first volume in a new series of technical monographs sponsored by the society's Electronic, Magnetic and Photonic Materials Division.

The thermomechanical fatigue failure of solder joints is increasingly becoming an important reliability issue for electronic packages. The purpose of this Laboratory Directed Research and Development (LDRD) project was to develop computational tools for simulating the behavior of solder joints under strain and temperature cycling, taking into account the microstructural heterogeneities that exist in as-solidified near eutectic Sn-Pb joints, as well as subsequent microstructural evolution. The authors present two computational constitutive models, a two-phase model and a single-phase model, that were developed to predict the behavior of near eutectic Sn-Pb solder joints under fatigue conditions. Unique metallurgical tests provide the fundamental input for the constitutive relations. The two-phase model mathematically predicts the heterogeneous coarsening behavior of near eutectic Sn-Pb solder. The finite element simulations with this model agree qualitatively with experimental thermomechanical fatigue tests. The simulations show that the presence of an initial heterogeneity in the solder microstructure could significantly degrade the fatigue lifetime. The single-phase model was developed to predict solder joint behavior using materials data for constitutive relation constants that could be determined through straightforward metallurgical experiments. Special thermomechanical fatigue tests were developed to give fundamental materials input to the models, and an in situ SEM thermomechanical fatiguemore » test system was developed to characterize microstructural evolution and the mechanical behavior of solder joints during the test. A shear/torsion test sample was developed to impose strain in two different orientations. Materials constants were derived from these tests. The simulation results from the two-phase model showed good fit to the experimental test results.« less

Chemical fluxes are typically used during conventional electronic soldering to enhance solder wettability. Most fluxes contain very reactive, hazardous constituents that require special storage and handling. Corrosive flux residues that remain on soldered parts can severely degrade product reliability. The residues are removed with chlorofluorocarbon (CFC), hydrochlorofluorocarbon (HCFC), or other hazardous solvents that contribute to ozone depletion, release volatile organic compounds into the atmosphere, or add to the solvent waste stream. Alternative materials and processes that offer the potential for the reduction or elimination of cleaning are being developed to address these environmental issues. Timing of the effort is critical, since the targeted chemicals will soon be heavily taxed or banned. DOE`s Office of Environmental Restoration and Waste Management (DOE/EM) has supported Sandia National Laboratories` Environmentally Conscious Manufacturing Integrated Demonstration (ECMID). Part of the ECM program involves the integration of several environmentally compatible soldering technologies for assembling electronics devices. Fluxless or {open_quotes}low-residue/no clean{close_quotes} soldering technologies (conventional and ablative laser processing, controlled atmospheres, ultrasonic tinning, protective coatings, and environmentally compatible fluxes) have been demonstrated at Sandia (SNL/NM), the University of California at Berkeley, and Allied Signal Aerospace-Kansas City Division (AS-KCD). The university demonstrations were directed under the guidance of Sandia staff.more » Results of the FY93 Soldering ID are presented in this report.« less

We present a new methodology for predicting the fatigue life of solder joints for electronics applications. This approach involves the integration of experimental and computational techniques. The first stage involves correlating the manufacturing and processing parameters with the starting microstructure of the solder joint. The second stage involves a series of experiments that characterize the evolution of the microstructure during thermal cycling. The third stage consists of a computer modeling and simulation effort that utilizes the starting microstructure and experimental data to produce a reliability prediction of the solder joint. This approach is an improvement over current methodologies because it incorporates the micro-structure and properties of the solder directly into the model and allows these properties to evolve as the microstructure changes during fatigue.

Previous chapters of this book have discussed the wetting behavior of near-eutectic Sn-Pb solders. These alloys are the most common in electronic applications and are deserving of the greatest attention. However, there are many applications where the properties of these alloys can be improved. A composite solder, or a solder that contains second-phase dispersions of particles, could improve solder joint properties. The area where composite solders could have the greatest impact is in improving the mechanical properties of the joint. However, the wetting behavior of the solder cannot be compromised for the sake of the mechanical properties -good wetting behavior is a necessity. Therefore, for a composite solder to be useful for electronic packaging applications mechanical properties, wetting and manufacturability must be optimized.

The challenge of keeping pace with emerging microelectronic device technologies has become increasingly difficult, and the fundamental limits of existing printed wiring board (PWB) technologies are becoming increasingly apparent. As a result, the domestic PWB industry now faces serious foreign competition from large, well-financed firms. The 1990 worldwide market for PWBs was $25.2 billion and has grown by just under 10% per year since 1988. North America’s demand is 28.5%, Japan’s is 27.6%, and Europe’s is 20.7%. The market is expected to grow to over $35 billion in 1993. The PWB industry in the U.S. consists of approximately 930 large companies. Of those, 600 have revenues of less than $5M/ year and 200 have revenues of between $5M and $25M/year. PWB technology is now approaching limitations that will have a profound effect on the ability to provide a means of utilizing the ever-increasing functionality that integrated circuits possess and promise. In addition, these limitations and increasing foreign competition will force many U.S. PWB companies out of business. One of the limiting processes referred to above is the age-old method of soldering.

The microstructural evolution of unpatterned Al-2wt.%Cu thin films has been examined to elucidate the mechanism by which copper improves electromigration resistance. After annealing at 425°C and cooling to room temperature at a rate of approximately 1°C/min., the microstructure of the Al-Cu films consisted of 1 μm aluminum grains with θ-phase Al2Cu precipitates at grain boundaries and triple points. The grain size and precipitation distribution did not change with subsequent isothermal heat treatments in the temperature range of 200° to 400°C. Al-Cu thin films annealed at 400°C, a temperature just below the Al/Al+θ solvus, exhibited microstructures in which the aluminum grain boundaries were depleted in copper except for the presence of the pre-existing large, widely dispersed AI2Cu precipitates. Al-Cu thin films annealed at 200° to 300°C were enriched with copper at the aluminum grain boundaries. The large, widely dispersed Al2Cu precipitates remained after the lower temperature anneals. From these results, it is proposed that the presence of copper in aluminum thin films improves electromigration resistance due to the precipitation of a thin film of Al2Cu, or a substoichiometric precursor, along the grain boundaries. The grain boundary phase retards grain boundary diffusion in the thin films, thereby reducing total mass transport and improving electromigration resistance.

Although solder technology’s roots are buried in antiquity, solder processing innovations are occurring at a faster pace than at any time in history. There are three primary drivers for this: rapidly changing design requirements, increasingly stringent process and product reliability requirements, and environmental issues. Improving solder processes to meet the needs of electronic manufacturing, while addressing a heightened awareness of environmental issues, including compliance to governmental regulations, is a great challenge to technologists supporting solder processes and will require the best efforts of multidisciplinary teams.

The distribution of copper in aluminum thin films is examined with respect to how the copper can influence electromigration behavior. Al-Cu thin films annealed in the single phase region, to just below the solvustemperature, have 0-phase Al2Cu precipitates at the aluminum grain boundaries. The grain boundaries between precipitates are depleted in copper. Al-Cu thin films heat treated at lower temperatures, within thetwo phase region, also have 0-phase precipitates at the grain boundaries but the aluminum grain boundariescontinuously become enriched in copper, perhaps due to the formation of a thin coating of 0-phase at the grain boundary. Here, it is proposed that electromigration behavior of aluminum is improved by addingcopper because the 0-phase precipitates may hinder aluminum diffusion along the grain boundaries. It was also found that resistivity of Al-Cu thin films decrease during accelerated electromigration testing prior to failure. Pure Al films did not exhibit this behavior. The decrease in resistivity is attributed to theredistribution of copper from the aluminum grain matrix to the 0-phase precipitates growing at the grain boundaries thereby reducing the number of defects in the microstructure.

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits (ICs). As the packing density of ICs increases, interconnect lines are required to carry ever higher current densities. Consequently, reliability due to electromigration failure becomes an increasing concern. Cu has been found to increase the lifetimes of these conductors, but the mechanism by which electromigration is improved is not yet fully understood. In order to evaluate certain theories of electromigration it is necessary to have a detailed description of the Cu distribution in the Al microstructure, with emphasis on the distribution of Cu at the grain boundaries. In this study analytical electron microscopy (AEM) has been used to characterize grain boundary regions in an Al-2 wt.% Cu thin film metallization on Si after a variety of thermal treatments. The results of this study indicate that the Cu distribution is dependent on the thermal annealing conditions. At temperatures near the θ phase (CuAl2) solvus, the Cu distribution may be modelled by the collector plate mechanism, in which the grain boundary is depleted in Cu relative to the matrix. At lower temperatures, Cu enrichment of the boundaries occurs, perhaps as a precursor to second phase formation. Natural cooling from the single phase field produces only grain boundary depletion of Cu consistent with the collector-plate mechanism. The kinetic details of the elemental segregation behavior derived from this study can be used to describe microstructural evolution in actual interconnect alloys.

The electromigration behavior of Sn–2.5Ag and Sn–0.7Cu (in wt %) flip chip solder joints on electroless NiP/Cu metallization at a current density of 1.3×104 A/cm2 was studied. For Sn-2.5 Ag solder, electromigration at 115 °C for 250 h showed a selective dissolution of Ni from the electroless NiP layer forming crystallized Ni3P. At 140 °C, the damage to the NiP layer was accelerated and instability of the NiP/Cu interface was observed. For eutectic Sn–0.7Cu solder, the electromigration behavior at a higher temperature was evaluated. At 180 °C, the NiP/Cu under bump metallurgy (UBM) started to show damage after 50 h. At 200 °C, the entire NiP/Cu layer was damaged, and P in the NiP layer moved to the edge of the anode much faster than the other species forming CuP2 intermetallics. NiP/Cu UBM experiences selective dissolution of Ni at lower temperatures, and the damage of the entire UBM occurred abruptly at the higher temperature.

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.

The need for increased speed and functionality by electronic components has pushed traditional electronic packages to the limit of their capabilities. Typically, the electronic device is electrically connected by wires or solder bumps in a package that gives the device environmental isolation and acts as a space transformer to transfer the electronic signals down leads to other discrete packaged devices on a printed circuit board. The discrete spacing of the devices and the time needed to propagate electronic signals along the wiring (that has a finite resistance and slows electron travel to a fraction of the speed of light) on the printed circuit board restricts the speed of the circuit. A promising solution is to use light, rather than electrons, to enhance signal transmission. The use of light, generated by lightemitting diodes (LEDs) or lasers, in these applications is called optoelectronic packaging. Applications in which optoelectronic packaging has had a significant impact include telecommunications (fiberoptic lines), optical reading devices (scanners), and supercomputers. The physics of transmitting signals via optics is well understood. However, there is a significant challenge in the area of interconnects. Interconnects are the interface between a transmission optics line and a device (Le., a laser or LED); they must be manufacturable and have excellent reliability. The difficulty with (and most expensive aspect of) optical interconnections is thatalignmentis critical. For multiple-mode optical interconnects, the alignment between the light source and the transmission line must be between 5 /lm and 10 /lm. In a singlemode interconnect, the alignment must be on the order of 1 /lm or less. The interconnects currently used for traditional electronic packages have nowhere near this requirement of alignment, being in the range of 50 to 100 /lm. Furthermore, accurate optical alignments represent up to 80 percent of the cost of the entire package. Therefore,innovativeapproaches to the materials used in optoelectronic packages-and their processing-are needed to enhance reliabil