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International audience; In this paper, SiGe nano-pillars coalescence was investigated using a 300 mm industrial Reduced Pressure-Chemical Vapor Deposition tool. An integration scheme based on diblock copolymer patterning provided nanometer size templates for the selective epitaxy of SiGe 25% nano-pillars. In order to study coalescence, thicknesses ranging from 20 to 35 nm were grown and samples characterized by Atomic Force Microscopy, X-Ray Diffraction, Scanning Spreading Resistance Microscopy and Transmission Electron Microscopy. The evolution in terms of grain shape, size and number was examined, with individual pillars merging into larger grains above 30 nm thickness. High degrees of macroscopic strain relaxation were obtained at the different stages of nano-pillars merging. Defects such as stacking faults and twins were identified as occurring at the early stages of nano-pillar coalescence.

Phase change memories use a specific phase change material (PCMat) as a resistor element for information storage. To obtain good reliability and performances of the device, interface between PCMat and electrodes needs to be optimized. In this work, we study the adhesion between the electrode material and GeTe PCMat by a mechanical characterization (four-point bending). Our results show that a thin titanium interfacial layer drastically enhances the adhesion energy. Using X-Ray Diffraction and Secondary Ion Mass Spectroscopy, strong chemical interactions between titanium and tellurium is evidenced. In particular, after a 400^oC anneal, Ti"3Te"4 formation is observed. This chemical affinity probably explains the improvement of adhesion between the electrode and GeTe.

In this work, we demonstrate for the first time the performance of polysilicon (poly-Si) NEMS fabricated with a low temperature process compatible with a NEMS above IC 3D integration. Most important figures of merit feature values still competitive in comparison to mono-crystalline (c-Si) NEMS: Allan deviation, quality factor (Q), Signal-to-Background ratio (SBR), Dynamic Range (DR), yield and variability, piezoresistive and elastic properties. We found the best process window (laser annealing conditions and dopant concentration) to optimize poly-Si NEMS with excellent features compared to conventional c-Si NEMS. The goal of this study is to replace c-Si for low cost 3D integration.

Accurate and reliable in-line monitoring of the different films thickness that occur throughout the integrated circuit manufacturing process is mandatory to develop and produce advanced microelectronic devices. X-ray reflectivity (XRR) is a fundamental and suitable metrology technique to precisely determine the thickness of both transparent and metallic thin films. Furthermore, XRR is very sensitive to surface and interface roughness, and also provides information about the film density. X-ray fluorescence (XRF) is currently used as a metrology technique to control the thickness and the elemental composition of relatively thick films. The performance of a new in-line metrology tool, which gathers XRR and XRF data to monitor film thickness, has been assessed. Results on the monitoring of high κ thin films, low κ materials, copper barrier and copper seed layers are presented.

Ge 2 Sb 2 Te 5 films sandwiched by ZnS–SiO 2 layers were studied by spectroscopic ellipsometry from room temperature up to 800°C. An irreversible modification of both materials is pointed out. ZnS cubic phase precipitation occurs after heating at 650°C, shown by grazing incidence X-ray diffraction. Chemical modification in phase change material is observed above 300°C, revealed by a typical behavior of a transparent layer.

Polysilicon etching is a critical process for VLSI. Recently1, HBr appeared to be the best choice for a good selectivity versus oxide and a good profile control. In this paper, we investigated a HBr-Cl2 chemistry in a classical RIE system at pressure below 15 Pa. The etching was performed with either resist or oxide masks. Results were optimized through statistical experimental designs. The influence of the different process parameters: power, pressure and gas flows were detailed. Etching of 100nm patterns, stopping within 70A thin gate oxide (even with a long overetch time) was achieved using the developped process.