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Access Memory) has many attractive properties such as small size, fast operation speed, and good endurance. However, MRAM has a relatively small TMR (Tunneling Magnetoresistance) ratio, which means a small on-off state separation. It is a challenge to set an optimal reference resistance to reliably differentiate “1” and “0” states. Several trimming circuits were suggested in the literature to adjust a reference value and its search range. The trim setting can be controlled manually by user input; however, it consumes huge test time and requires off-chip engineering analysis to search and apply a trim setting for an individual memory array. In this paper, we will discuss the recent silicon results of fully automated trim process leveraging existing MBIST (Memory Built-in Self-Test) resources and new features to accommodate more complicated multi-step reference setting implementation through minor update of an existing MBIST circuit. The proposed MBIST solution uses a minimal number of tests to analyze massive array properties and automatically set complicated multi-step trim settings within a chip without the need for an external tester or manual adjustments.

In this paper we present a read circuitry that tackles all STT-MRAM read challenges. First, a negative temperature coefficient (NTC) reference based on an MTJ in series with an “NTC” resistor circuit emulator is described. Then, an offset cancelled voltage sense amplifier using low read current and reference averaging is discussed. Measurement results show a maximum of 2% reference impedance error (vs. ideal) and 1.7% read error rate degradation (vs. technology intrinsic defectivity rate). A 14.7Mb/mm2 memory density is also achieved, which is the best STT-MRAM published density for embedded applications.

Spin Transfer Torque Magneto-resistive Random- Access Memory (STT-MRAM) is emerging as a promising substitute for flash memories due to scaling challenges for flash in process nodes beyond 28nm. STT-MRAM’s high endurance, fast speed and low power makes it suitable for wide variety of applications. An embedded MRAM (eMRAM) compiler is highly desirable to enable SoC designers to use eMRAM instances in their designs in a flexible manner. However, the development of an eMRAM compiler has added challenges of handling multi-fold higher density and maintaining analog circuits accuracy, on top of the challenges associated with conventional SRAM memory compilers. In this paper, we present a successful design methodology for a high density 128Mb eMRAM compiler in a 28nm fully depleted SOI (FDSOI) process. This compiler enables optimized eMRAM instance generation with varying capacity ranges, word-widths, and optional features like repair and error correction. eMRAM compiler design is achieved by evolving various architecture design, validations and characterization methods. A hierarchical and modular characterization methodology is presented to enable high accuracy characterization and industry-standard EDA view generation from the eMRAM compiler.

The input-referred offset of a dynamic latch-based sense amplifier for resistive memories is extensively analyzed. This circuit is modeled using both small and large signal analysis, in order to evaluate mismatch effects and to support design robustness to process variations. Effect of various design parameters on offset are studied and reported. It is shown that load capacitance has a profound effect on the sense amplifier offset. Design optimization is then proposed thanks to this analysis, resulting to an input-referred offset (simply called offset in the rest of the paper) down to about 200 Ohms for one sigma variation with 20fF applied load capacitance.

This paper describes an integrated SRAM standby power reduction design in a 40nm low power process. It features a closed-loop array leakage control with floating bitlines, reducing 46% of leakage current. It relies on self-refreshing virtual VDD clocked by a PVT-compensated SRAM worst-case data retention sensor. The concept is implemented in a 256kbit SRAM with a 0.242µm2 6T cell.