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This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiple-input single-output current-mode shadow filter and oscillator using current-controlled current conveyors (CCCIIs). The CCCII current gains are used to set the filter's quality factor and natural frequency. The filter is resistorless with grounded capacitors, making it more suitable for integration. The filter offers low-pass, high-pass, band-pass, band-stop and all-pass transfer functions in a single topology by appropriately applying the input signals. To validate the functionality of the new topology, the proposed circuit is simulated by SPICE using bipolar transistors arrays AT&T ALA400-CBIC-R. [ABSTRACT FROM AUTHOR]

This paper presents a new current-mode first-order versatile active filter employing one extra-x second-generation current controlled current conveyor (EX-CCCII) and one grounded capacitor. The proposed filter can realize first-order filtering functions of a low-pass filter (LPF), high-pass filter (HPF), and all-pass filter (APF) within the same topology with low-input and high-output impedances required for current-mode circuits. This multiple-output EX-CCCII-based filter can provide six transfer functions as both non-inverting and inverting filtering functions of the LPF, HPF, and APF are obtained. The filter also offers electronic control of the pole frequency of all filtering. The proposed current-mode filter can be applied to work as a mixed-mode active filter, namely in the transadmittance-mode (TAM), transimpedance-mode (TIM), and voltage-mode (VM). Each operation mode can provide six transfer functions. The proposed filter was simulated and designed using SPICE and 0.18 µm CMOS technology. Experimental results using the commercially available integrated circuit AD844 were used to confirm the functionality of the new circuits. [ABSTRACT FROM AUTHOR]

This paper presents a novel multiple-input and multiple-output current-mode universal analog filter with electronic tuning capability. The proposed circuit uses a single second-generation current-controlled current conveyor with extra-X terminals (EX-CCCII) and two grounded capacitors. The filter can offer five standard filtering functions, namely low-pass, high-pass, band-pass, band-stop, all-pass responses, in the same circuit without changing the internal configuration of the filter by selecting appropriate input and output signals. To obtain the five standard filtering functions, inverted input signal and input matching conditions are absent. The natural frequency of all filter responses can be electronically controlled. The proposed circuit was simulated by SPICE using 0.18 μm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC). The results of experiments using the integrated circuit operational amplifier AD844 confirm the functionality of the new filter. [ABSTRACT FROM AUTHOR]

This work describes voltage-mode (VM), current-mode (CM) PID controllers and an electrically controllable floating inductance (FI) simulator circuit. Only a single current-controlled current backward transconductance amplifier (CC-CBTA) and a grounded capacitor are used in the proposed FI simulator circuit. One CBTA, one CC-CBTA, two capacitors and one resistor are used in the proposed PID controllers. All of the proposed circuits have appropriate input and output impedance values, allowing them to be utilized in cascade connections without requiring a buffer circuit. There is also no matching constraint between the active and passive values of the proposed circuit. The SPICE software environment and experimental results were used to validate theoretical derivations and associated outcomes. The layout of the CC-CBTA has been built, and the post-layout simulations are carried out using the netlist extracted from the layout. Comparisons were made with similar circuits found in the professional literature. [ABSTRACT FROM AUTHOR]

This paper reports on the design, implementation, and characterization of a current-mode analog-front-end circuit for capacitance-to-voltage conversion that can be used in connection with a large variety of sensors and actuators in industrial and rehabilitation medicine applications. The circuit is composed by: (i) an oscillator generating a square wave signal whose frequency and pulse width is a function of the value of input capacitance; (ii) a passive low-pass filter that extracts the DC average component of the square wave signal; (iii) a DC-DC amplifier with variable gain ranging from 1 to 1000. The circuit has been designed in the current-mode approach by employing the second-generation current conveyor circuit, and has been implemented by using commercial discrete components as the basic blocks. The circuit allows for gain and sensitivity tunability, offset compensation and regulation, and the capability to manage various ranges of variations of the input capacitance. For a circuit gain of 1000, the measured circuit sensitivity is equal to 167.34 mV/pF with a resolution in terms of capacitance of 5 fF. The implemented circuit has been employed to measure the variations of the capacitance of a McKibben pneumatic muscle associated with the variations of its length that linearly depend on the circuit output voltage. Under step-to-step conditions of movement of the pneumatic muscle, the overall system sensitivity is equal to 70 mV/mm with a standard deviation error of the muscle length variation of 0.008 mm. [ABSTRACT FROM AUTHOR]

In this communication, a low-voltage complementary metal-oxide semiconductor (CMOS) current-mode full-wave rectifier (FWR), implemented from a flipped voltage follower-biased MOS translinear loop (FVF-MTL) is presented. The use of flipped voltage follower (FVF) minimizes the overall supply voltage demand by reducing the voltage headroom while maintaining the operation of the MOSFETs in strong inversion mode. The functioning of the proposed FWR circuit has been demonstrated through simulations carried out on Cadence Virtuoso software at 0. 1 8 μ m CMOS technology at a supply voltage of 0.85 V. The proposed FWR works over an input range of ± 2 0 0 μ A with a maximum linearity error of 3% in its transfer characteristics. The -3 dB bandwidth of the circuit has been found to be 54.95 MHz. The minimum power and maximum power consumed by the circuit are 22.6 nW and 4 1 5 μ W , respectively. Post-layout simulations, Monte Carlo (MC), corner and temperature analyses have been carried out to estimate the performance and robustness of the proposed circuit. [ABSTRACT FROM AUTHOR]

This paper presents a novel current-mode true RMS–DC converter based on the dynamic translinear principle. The converter is designed using a third-order translinear loop, resulting in a very compact and simple circuit. The proposed circuit is designed in 65 nm CMOS technology, operates with 1 V power supply, has only 14 transistors and performs satisfactorily over a wide input current range of 300 nA–950 nA and for a frequency range of 600 Hz–650 kHz for a capacitance value of 10 nF. The frequency range of operation can be tuned by varying the external off chip capacitor and the bias current. The circuit consumes 20 nW static power, 1.6 μW maximum dynamic power and offers the lowest FOM among the other RMS–DC converter circuits presented in the literature. Comprehensive mathematical analysis along with the post layout simulation results confirm the validity of the proposed circuit. To test the use of converter in real world scenarios, the proposed converter is introduced within a typical ECG detection system and the results show that the circuit is an attractive solution for RMS–DC conversion in low-voltage low-power applications. [ABSTRACT FROM AUTHOR]

With the rising prevalence of wearable biomedical devices for recording diverse biosignals, the potential for inaccurate interpretations due to noise susceptibility, including false alarms and misdiagnoses, is increasingly recognized. This study presents the systematic design and evaluation of a current-mode-based active notch filter aimed at eliminating the pervasive power-line interference (PLI) that corrupts biosignals. The filter is constructed using a modern and versatile current-mode analog building block (ABB), specifically the voltage differencing gain amplifier (VDGA). The design of this second-order filter incorporates a single VDGA as an active component and two capacitors as passive components, eliminating the need for resistors. Employing this filter, the influence of the 50Hz PLI on biological signals is effectively suppressed. The filter exhibits desirable properties of the current-mode circuit, including reduced power consumption, an expanded dynamic range, and enhanced accuracy. Key parameters of the filter, such as the pole frequency and the quality factor, can be electronically adjusted and orthogonally tuned via the bias currents of the VDGA. To validate its functionality, the proposed filter design was simulated using the PSPICE simulator with the MAX435 IC's macro-model. The simulation results revealed a notch depth and total harmonic distortion (THD) of -52.9 dB and -55 dB, respectively. The performance of this filter was subsequently compared with existing analog notch filters detailed in the literature. Given its efficacy and simplicity, the proposed filter is deemed suitable for deployment in high-performance biomedical detection equipment. [ABSTRACT FROM AUTHOR]

Copyright of Informacije MIDEM: Journal of Microelectronics, Electronic Components & Materials is the property of MIDEM Society and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Summary: This work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topology has low static power consumption compared with traditional current‐mode circuit topology implementations, thanks to the discrete nature of the current‐steering hybrid topology. The proposed scheme is implemented in 1.2 V, 65‐nm complementary metal‐oxide semiconductor (CMOS). The performance results show that the link training scheme sets the control bits for both the transmitter driver and hybrid circuit topology when the backchannel adaptation loop gets locked for 1‐ and 3‐mm interconnects for process, voltage, and temperature (PVT) variations. The proposed hybrid circuit topology is able to receive the required far‐end transmitted data with the link training scheme and has the differential recovered received signal voltage swing of 1.2 V for both 1‐ and 3‐mm interconnect at the 10‐Gb/s data rate. The total power consumption of the hybrid is 3 and 3.5 mW for 1‐ and 3‐mm interconnect with an energy efficiency of 0.6 and 0.7 pJ/bit, respectively, at 10‐Gb/s full‐duplex operation. [ABSTRACT FROM AUTHOR]

This paper offers a new current-mode first-order versatile filter employing two translinear current conveyors with controlled current gain and one grounded capacitor. The proposed filter offers the following features: realization of first-order transfer functions of low-pass, high-pass, and all-pass current responses from single topology, availability of non-inverting and inverting transfer functions for all current responses, electronic control of current gain for all current responses, no requirement of component-matching conditions for realizing all current responses, low-input impedance and high-output impedance which are required for current-mode circuits, and electronic control of the pole frequency for all current responses. The proposed first-order versatile filter is used to realize a quadrature sinusoidal oscillator to confirm the advantage of the new topology. To confirm the functionality and workability of new circuits, the proposed circuit and its application are simulated by the SPICE program using transistor model process parameters NR100N (NPN) and PR100N (PNP) of bipolar arrays ALA400-CBIC-R from AT&T. [ABSTRACT FROM AUTHOR]

This paper introduces the use of an extra X current conveyor (EXCCII) for realizing logic operations, suited for mixed signal design, without necessitating separate digital blocks. The NOR and OR logic functions are thus shown to be realized using the current-mode analog building block operable at a low voltage. The use of ± 0. 7 5 V supply makes the new circuits operable at low voltage. The EXCCII bias current used in the design is 25 μ A. The input currents for defining logic 0 and logic 1 are, respectively, taken as 0 mA and 0.5 mA. The proposed circuits' delay is found to be 10 ns for low-to-high transition, while 2 ns for high-to-low transition for NOR gate under capacitive loading conditions. The use of the current-mode approach makes the new proposed circuit apt for current-mode signal processing. The new proposed logic function circuits are compatible with analog circuits, thus providing an easy merger for mixed signal systems design, paving the way to a modular design approach. As an extended application in artificial neural networks, the proposed circuit is shown to generate a sigmoid activation function with convincing results. Several results are included by varying the reference current, and the circuit's robustness aspect is also tested in the presence of fluctuation in the bias current of EXCCII. The novel approach of utilizing an analog building block for realizing digital functions is, therefore, verified with promising future applications. [ABSTRACT FROM AUTHOR]

Abstract Experimental data on analog performance of gate‐all‐around III‐V vertical Tunnel Field‐Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current‐mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large‐signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage.

Copyright of Journal of Zhejiang University (Science Edition) is the property of Journal of Zhejiang University (Science Edition) Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Abstract A full‐wave rectifier based on a modified voltage differencing transconductance amplifier‐MVDTA and four n‐MOS transistors (or inverting full‐wave rectifier), with no use of any passive elements is proposed in this paper. The proposed design is suitable for a low voltage and high frequency input voltage/current signal. The used MVDTA possesses certain new connections without any changes in the original circuit resources of VDTA. The proposed configuration possesses satisfactory zero crossing performance, excellent linearity, low component count―a simple and compact structure―which makes it an adequate candidate for implementation in the form of IC circuits. The amplitude‐waveform of the current/voltage rectified signal at the output of the proposed circuit can be electronically controlled by the applied bias currents. The influence of possible non‐ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. To verify the validity of the presented circuits, SPICE simulations deploying 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V are reported, fully consistent with the theoretical predictions. The noise and Monte Carlo analyses were also performed in order to obtain further insight into the robustness of the proposed design. The proposal is also supported by experimental results in order to confirm the workability of the proposed solution.

Enhancing the electromagnetic interference (EMI) resistance of electronic systems has emerged as a critical focus of research with the growing complexity of the electromagnetic environment. In the context of deep submicron processes, the current-mode CMOS circuits exhibit several advantages, including high speed, low power consumption, and superior noise immunity. Thus, we propose an improved conventional current-mode CMOS inverter and a current-mode CMOS Schmitt inverter based on the principles of threshold arithmetic algebra system. Simulation and printed circuit board (PCB) testing results indicate that the designed Schmitt inverter improves immunity of the conventional inverter to pulsed and sine wave interference. Additionally, the simulation results reveal that Schmitt inverter exhibits a greater resilience to sine wave interference than pulsed wave interference, and the higher the frequency of the interfering signals, the greater the current-mode CMOS Schmitt inverter's immunity. [ABSTRACT FROM AUTHOR]

Experimental data on analog performance of gate‐all‐around III‐V vertical Tunnel Field‐Effect Transistors (TFETs) and circuits are presented. The individual device shows a minimal subthreshold swing of 44 mV/dec and transconductance efficiency of 50 V−1 for current range of 9 nA/μm to 100 nA/μm and at a drain voltage of 100 mV. This TFET demonstrates translinearity between transconductance and drain current for over a decade of current, paving way for low power current‐mode analog IC design. To explore this design principle, a current conveyor circuit is implemented, which exhibits large‐signal voltage gain of 0.89 mV/mV, current gain of 1nA/nA and an operating frequency of 320 kHz. Furthermore, at higher drain bias of 500 mV, the device shows maximum transconductance of 72 μS/μm and maximum drain current of 26 μA/μm. The device, thereby, can be operated as a current mode device at lower bias voltage and as voltage mode device at higher bias voltage. [ABSTRACT FROM AUTHOR]

In this paper, an analog current-mode circuit with low power consumption and low area is designed and implemented to detect the QRS complexes from the ECG signal. An efficient algorithm is proposed for this purpose which uses the energy operator. This algorithm is fully implemented in the analog domain with the transistors operating in the subthreshold region, resulting in ultra-low power consumption. The proposed method is evaluated with the data contained in the standard MIT-BIH arrhythmia database and reaches the acceptable values of 98.53% for the average accuracy, 99.41% for sensitivity and 99.13% for positive prediction. The proposed circuit is implemented in 0.18 μm CMOS technology with a power supply of 1.8 V. Using this circuit, there is no need to use an analog-to-digital converter in the detector system, which can lead to more reduction in the power consumption and area of the system. With power consumption of 15.77 nW and area of 0.078 mm2, this circuit is suitable for using in wearable and implantable applications. • This structure is a fully-analog QRS-detector realized by using current-mode circuits. • The circuit attains an ultra-low power and low area while has an acceptable accuracy. • The proposed circuit has an error rate of 1.47% and consumes 15.77 nW. • Analog-to-digital converter can be omitted for heart-rate monitoring in this design. • The circuit output can be used for efficient sampling, Transmitting and processing. [ABSTRACT FROM AUTHOR]

Summary: This work proposes a power‐efficient half‐rate current‐integrating logic (CIL) echo cancelation hybrid circuit topology for full‐duplex communication for off‐chip interconnects in 65 nm CMOS. The proposed hybrid topology has a low power consumption compared to traditional current‐mode hybrid circuit topology implementations, thanks to the CIL hybrid topology with sample and hold front‐end. The post‐layout performance of the half‐rate CIL hybrid includes package parasitic has a differential received signal voltage swing of 190 mV at 10 Gb/s data rate with a timing jitter of 16 ps over a 20 cm FR4 PCB interconnect. The total power consumption of the half‐rate CIL hybrid is only 2 mW, and its energy efficiency is 0.4 pJ/bit. The layout of the hybrid occupies an area of 0.0008 mm2. [ABSTRACT FROM AUTHOR]

This article presents a transimpedance amplifier (TIA) design suitable for 1 Gbps operation using a 4-level pulse amplitude modulation scheme. It is aimed toward communication protocols with large-area photodetectors, such as plastic-optical-fiber, visible light communications, and biomedical applications. The TIA leverages a flipped-voltage-follower as well as global current feedback to extend the bandwidth of the TIA and operates up to 400 MHz with a very low static power while driving a very large capacitance. The TIA has a static power consumption of only 1.2 mW at a 1 V supply voltage. Additionally, the fully-differential version of the proposed TIA is introduced in the case of using spatially-modulated light detectors. The design is validated with post-layout simulations employing a commercially available 40 nm CMOS process. Mismatch and corner simulations demonstrate that the proposed TIA can still provide the specifications in the worst-case scenarios. [ABSTRACT FROM AUTHOR]

This article contributes a new configuration of the current mode (CM) sinusoidal oscillator employing a single voltage differencing transconductance amplifier (VDTA), as an active building block, and all grounded passive elements. This fully electronically tunable circuit offers independent control of its design parameters i.e., oscillation condition (OC) and oscillation frequency (OF). To validate the design concept, along with the regular mathematics, simulations have been performed using PSPICE software. Experimental results have been obtained by the commercially available IC i.e., LM13700, to validate the theoretical expectations. [ABSTRACT FROM AUTHOR]

An approach to realising logic functions using analog building block is explored, with promising results in form of OR and NOR functions being tested with EXCCII as basic building current-mode block. The other functions like NAND and AND realisation is also presented. The proposed circuits employ current-mode operation and show low input and high output impedance, which makes these designs practically useable. The approach is expected to benefit the mixed signal design, without necessitating separate conventional digital blocks. Several possible application areas are thus suggested. PSPICE simulation results are shown in support of the proposed idea. [ABSTRACT FROM AUTHOR]

This letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1 MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies. The impact of non‐idealities and parasitic effects on the circuit performance was thoroughly investigated; however, the absence of passive elements ensured that any parasitic effects remained negligible. The simulation results obtained using 0.18‐μm CMOS technology and a ±0.9 V supply voltage were consistent with theoretical predictions, validating the efficacy of the proposed design. [ABSTRACT FROM AUTHOR]

This study introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The fundamental components of the architecture include current-mode circuits, representing the class, and a voltage-mode comparator. Specifically, the current mode circuits comprise the Mahalanobis distance circuit, Sigmoid function circuit, analog multiplier, and current mirrors. Regarding the voltage comparator, which receives the final decision, a folded-cascode operational amplifier is employed. The operational principles of the architecture are extensively explained and applied in a power-efficient configuration (operating under 976nW) with low power supply rails (0.6 V). The proposed implementation is tested on real-world biomedical classification tasks, achieving classification accuracy exceeding 91.6%. The designs are implemented using a 90 nm CMOS process and developed using the Cadence IC Suite for both schematic and layout design. Monte-Carlo analysis, encompassing both process and mismatch, as well as corner analysis, are provided to confirm the robust characteristics of the proposed classifier. Through comparative analysis of post-layout simulation results with an equivalent software-based classifier and related literature, the proper operation of the proposed architecture is confirmed. [ABSTRACT FROM AUTHOR]

A full‐wave rectifier based on a modified voltage differencing transconductance amplifier‐MVDTA and four n‐MOS transistors (or inverting full‐wave rectifier), with no use of any passive elements is proposed in this paper. The proposed design is suitable for a low voltage and high frequency input voltage/current signal. The used MVDTA possesses certain new connections without any changes in the original circuit resources of VDTA. The proposed configuration possesses satisfactory zero crossing performance, excellent linearity, low component count―a simple and compact structure―which makes it an adequate candidate for implementation in the form of IC circuits. The amplitude‐waveform of the current/voltage rectified signal at the output of the proposed circuit can be electronically controlled by the applied bias currents. The influence of possible non‐ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. To verify the validity of the presented circuits, SPICE simulations deploying 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V are reported, fully consistent with the theoretical predictions. The noise and Monte Carlo analyses were also performed in order to obtain further insight into the robustness of the proposed design. The proposal is also supported by experimental results in order to confirm the workability of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180 nm CMOS process and operating with ± 1.8 V supply rails, the input resistance is 1.05 ohms and the power dissipation is 93.6 µW. The bandwidth, for a gain of 100 dBohm, exceeded 9 MHz. For a 1µA, 1 MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09 pA/√Hz and with a photodiode capacitance of 2pF is 8.52 pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5 to 2 pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned. [ABSTRACT FROM AUTHOR]

This research article explores the possible applications of voltage differencing current conveyor (VDCC), as a current mode universal filter and a sinusoidal oscillator. Without the need for an additional active/passive element, a very simple hardware modification makes it a dual-mode quadrature oscillator from the filter configuration. Both the proposed circuit requires only two VDCC and all grounded passive elements, hence a preferable choice for integration. The filter has some desirable features such as availability of all five explicit outputs, independent tunability of filter parameters. Availability of explicit quadrature current outputs, independence in start and frequency of oscillations, makes it a better oscillator design. Apart from prevalent CMOS simulation results, VDCC is also realized and experimentally tested using the off-the-shelf integrated circuit. All the pen and paper analysis such as non-ideal, sensitivity and parasitic analysis supports the design. [ABSTRACT FROM AUTHOR]

This paper proposes low voltage/power, current-mode second-order Butterworth high-pass filter design in the sinh-domain for biomedical applications. The proposed filter is a continuous-time filter in the companding-class. Sinh-domain filters have the advantages of electronically adjusting the frequency response without the need for non-chip capacitors and full integration on the chip, providing low power consumption and offering a high dynamic range. These advantages of the sinh-domain are beneficial for biomedical applications due to its low power consumption requirement. The proposed filter topology is suitable for eliminating low-frequency interferences of biomedical signals like electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG). In the realization of this filter, the method of simulation of passive elements with sinh-domain cells is used. The proposed high-pass filter in the 0.05 Hz-20 Hz operating frequency range with a 0.5 V power supply shows the power dissipation of 12.5 nW while its dynamic range exceeds 60 dB. Additionally, no resistances are used in the proposed topology. Simulations have been performed by using OrCAD Capture CIS to demonstrate the performance of the filter. These simulations have been implemented with the TSMC 0.25 µm CMOS process parameters. [ABSTRACT FROM AUTHOR]

Some time back, Kircay reported an electronically-tunable current-mode square-root-domain first-order filter capable of realizing low-pass (LP), high-pass (HP) and all-pass (AP) filter functions. When simulated in SPICE, Kircay's circuit has been found to exhibit DC offsets in case of LP and AP responses and incorrect transient response in case of HP response. In this paper, an improved circuit overcoming these difficulties/deficiencies has been suggested and its workability of the improved circuit as well as its capability in meeting the intended objectives has been demonstrated by SPICE simulation results. [ABSTRACT FROM AUTHOR]

In this study, a new current-mode fractional-order universal filter is presented by using multi mode second generation current controlled current conveyors (MO-CCCII). The circuit consists of two resistors and grounded capacitors with only three MO-CCCII. This is accomplished with a fractional-order capacitor, also known as a stationary phase element, to form a fractional-order filter. The value of this capacitor depends only on the fractional-order α (0 < α < 1). The proposed filter is designed as fractional (1 + α) = 1. 5 , 1.8 and 1.9 order. The fractional-order capacitor is obtained using the Foster-I R C network circuit. The filter is simulated with BJT-based MO-CCCII using PSPICE simulation program for the filter to verify the theory and to show the performance of it. The fractional-order universal filter outputs are provided the desired stop band attenuation and more precise control of attenuation slope. Through the fractional-order parameter, it is revealed that the filter designer can fully meet the requirements of the filter. It also offers design flexibility since the frequencies of interest depend not only on circuit components but also on fractional-order parameters. [ABSTRACT FROM AUTHOR]

A high-performance CMOS, fully balanced second-generation current conveyor (FBCCII) is proposed to exclusively use CCII circuits in integrated circuit applications. In the proposed circuit, a current folding technique is applied to a fully balanced version of transconductance amplifier. The proposed FBCCII consumes 84 μ W of power and has an open-loop gain of 47.83 dB with 62.9 ∘ of phase margin. The simulated input referred noise is 155 nV/ Hz @ 1 KHz and has a unity gain bandwidth of 39.8 MHz. A common mode feedback (CMFB) circuit is also proposed to improve the dynamic range of the proposed FBCCII circuit by 50 % as compared to the circuit with-out CMFB. The CMFB consumes 170 μ W of power and has a bandwidth of 60 MHz. The proposed circuit is simulated using standard 180 nm CMOS process operating at ± 0.5 V supply voltage. To verify the effectiveness of the approach, a fully differential variable gain amplifier with tunable gain from 0 to 30 dB is designed. Also, a bandpass filter with quality factor = 4 and bandwidth of 10 MHz is designed using the proposed FBCCII. A novel low-pass filter (LPF) using the proposed FBCCII is designed for bio-medical applications. The proposed LPF is a second-order filter with the cut-off frequency of 55 Hz and 121 nV/ Hz of input-referred noise. The LPF is designed at a supply voltage of ± 0.5 V, and the spurious free dynamic range of proposed LPF is 85 dB. The figure of merit of the LPF is 7.3 fJ. The layout area of the proposed FBCCII design is 6889 μ m 2 ( 83 μ m × 83 μ m ). [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a novel current output stage (COS) is introduced. Deliberately compose of class AB operation and a special voltage sense and current compensation scheme enables the structure to operate at extreme voltage beyond the triode limits to achieve wide voltage dynamic range and grants it such following ever demanded merits at power supplies of 1.8V: low power consumption of 40 µW, high drive to bias current ratio of 100. The results are verified by Spectre post-layout simulation using 0.18 µm CMOS standard technology of TSMC. The process, the stability and robustness of the proposed COS are verified by stepwise response and Monte Carlo and corner simulations, respectively. [ABSTRACT FROM AUTHOR]

This article is devoted to a new circuit proposal for precision rectification, which is designed using current feedback operational amplifiers. The new proposed circuit operation is clearly discussed, circuit analysis is performed and the workability is verified through extensive simulations carried out using PSPICE software. The in-built model library of used current feedback operational amplifier (namely, AD844) is used for simulating the proposed circuit. The performance metrics for the proposed circuit, which are verified includes signal precision of 100 mV, signal frequency of 1 MHz and linearity range of ±200 mV and output adjustment through auxiliary scaling block. Other features include low output impedance (100 Ω) for voltage mode cascading, high input impedance for one-half cycle of input, and employment of grounded resistors only. These features are apt for proposed circuit's actual application perspective for voltage-mode analog design, since cascading requirements are easily fulfilled and use of grounded resistors benefit integration aspects. [ABSTRACT FROM AUTHOR]

In this paper a high-performance low-voltage low-power CMOS second-generation current conveyor (CCII) is presented. The proposed CCII is based on super transistor (ST) and enables low input impedance at X terminal and high output impedance at Z terminal. It also utilizes a novel power saving strategy in which a single NMOS cascode current mirror conveys X terminal current to Z terminal, provides high impedance at Z terminal and reduces the X terminal impedance all together resulting in a low-power and compact structure. As another advantage, only NMOS transistors are used in processing voltage and current signals granting the proposed CCII high frequency operation. PMOS transistors are used only for biasing. However, the proposed CCII cannot provide infinite impedance at Y terminal. HSPICE simulations using 0.18 µm parameters and supply voltage of ±0.9 V confirms that the proposed CCII exhibits impedances of 0.155 Ω, 1.6 MΩ and 47 kΩ at X, Z and Y terminals, respectively. Voltage and current bandwidths are also 377 MHz and 159 MHz, respectively. Some of the applications of the proposed CCII are given. DOI: http://dx.doi.org/10.5755/j01.eie.24.2.17948

A compensated pyroelectric infrared (PIR) detector based on Mn‐doped 0.15Pb(In1/2Nb1/2)O3‐0.55Pb(Mg1/3Nb2/3)O3‐0.30PbTiO3 (Mn‐PIMNT(15/55/30)) relaxor ferroelectric single crystal was theoretically designed and experimentally fabricated. Under the current‐mode amplification circuit, the voltage responsivity and specific detectivity of the compensated detector reached 8 × 104 V/W@10 Hz and 3.6 × 108 cm⋅Hz1/2/W, respectively. The noise mechanism of the detector was studied and the dominant noise sources at different frequencies were simulated. Even though the noise density of the compensated detector increased due to the introduction of the parallel compensation element, substantially enhanced signal stability was achieved and the compensated detector was much less susceptible to environmental temperature changes and vibrations, which is more suitable for application in harsh environments. [ABSTRACT FROM AUTHOR]

This paper presents the design, simulation and implementation of a small scale battery charger with low harmonic distortion in current. It was proposed a design composed of two boost converters in cascade, the first operating as PFC and second as a regulator of the injected current to the batteries. Additionally, it was presented the procedure for the controllers design of each stage. In the first stage was used a control in average current mode and in the second stage were used two controls that enable you to employ the method of constant current - constant voltage in order to charge the batteries. In both stages were used the PI controllers and with the power electronic circuit were simulated in the PSIM® and MATLAB® software and validated experimentally In this tests, power factors close to 0.98 and harmonic distortion in current below 10% were obtained, complying with the requirements of the IEC 61000-3-2 standard. Finally, the conclusions are presented. [ABSTRACT FROM AUTHOR]

The study discusses selected issues of modelling and designing current‐mode devices. The authors propose the design flow that covers abstract behavioural models, the schematic and SPICE‐level netlists and the post‐layout parasitic parameters. The considerations related to the analogue functional blocks with a dual‐stage complexity. The theoretical backgrounds of the current‐mode basic building blocks are introduced. Special attention has been paid to a new current‐mode active component, digitally programmable modified current differencing transconductance amplifier (MCDTA). Based on the idea of an MCDTA, the authors have developed their own cell, which integrates the digital control feature (programmability) into current‐mode analogue devices. This original solution enables the dual control techniques, coarse digital control and precise analogue control to be used. The presented examples of continuous‐time active filters show that such a solution enables flexibility in the digital control of the parameters of analogue blocks. In order to facilitate the integration of the analogue and mixed‐signal models in a single environment, VHSIC Hardware Description Language ‐ Analogue Mixed Signal (VHDL‐AMS) language was selected for the behavioural modelling methodology. The authors have used the back annotating mechanism to update behavioural models based on an estimation of the post‐layout parameters. The approach is presented on examples that were implemented in TMSC 40 nm complementary metal–oxide–semiconductor technology. [ABSTRACT FROM AUTHOR]

Three simulated floating inductor (SFI) circuits containing a single DDCC− called as minus‐type differential difference current conveyor are proposed. These SFIs are series lossy, parallel lossy and negative lossless ones. The used DDCC− in each of the proposed SFIs has a single Z terminal. Without needing any passive element matching constraints, each of the proposed SFIs is composed of a minimum number of passive elements. As application examples, second‐order current‐mode (CM) and voltage‐mode low‐pass (LP) filters derived from the proposed series lossy SFI are given. Also, a fourth‐order CM Butterworth LP filter example is presented as another application. A second‐order CM high‐pass (HP) filter and an RLC resonant circuit obtained from the proposed parallel lossy SFI are given. All the simulations are achieved via SPICE program. Moreover, some experimental results for the proposed lossy SFIs and CM HP filter are given in order to show the performances. [ABSTRACT FROM AUTHOR]

A new plus‐type second‐generation voltage conveyor (VCII+) based first‐order mixed‐mode (MM) all‐pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current‐mode selection while it has low input and low output impedances for the transimpedance‐mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non‐ideal analysis by taking into account all the parasitic resistors and non‐ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 μm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters. [ABSTRACT FROM AUTHOR]

The authors propose a hybrid transceiver and an energy‐efficient link architecture for bidirectional multipoint‐to‐multipoint signalling across on‐chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall energy efficiency of the link. Also, compared to existing passive terminated interconnect with current‐mode receivers at all the points, the proposed link deploys low impedance current‐mode receivers providing active terminations at both the ends of the interconnect and high‐impedance voltage‐mode receivers, which do not consume any portion of the signalling current, at the intermediate nodes of the interconnect which further lowers the required transmitter signalling current. A mixed‐mode or hybrid transceiver architecture has been proposed for the aforementioned link, which can act either as a current‐mode transmitter or a current‐mode receiver or a voltage‐mode receiver. The architecture has been implemented in 0.18‐μm complementary metal oxide semiconductor technology for an interconnect of length 4 mm and having five transceiver nodes. The total energy efficiency of the architecture is 0.70 pJ/b for a speed of 3.0 Gb/s. [ABSTRACT FROM AUTHOR]

This article presents a majority-logic device, called sttMAJ, based on spin-transfer torque magnetic tunnel junctions (STT-MTJs). sttMAJ devices make it possible to build Boolean and non-Boolean circuits without any transistors. We leverage a physics-based model of sttMAJ device to the design of different highly scalable current-mode logic circuits and neuromorphic-computing/image-processing applications. The functionality of sttMAJ-based circuits is verified using the SPICE circuit simulator. The simulation results reveal that the gate device not only provides a simple and powerful structure (in terms of implementing digital functions and image-processing applications with a small number of devices) but also offers high performance due to its better electrical properties. [ABSTRACT FROM AUTHOR]

This paper presents grounded and floating memristor emulators based on current differencing transconductance amplifier. These emulators are realized using current differencing transconductance amplifier, operational transconductance amplifier and a grounded capacitor. Incremental to decremental memristor emulators and vice versa are easily obtained by modifying the circuit slightly. These memristor emulators are very simple in design over other complex realizations reported in the literature. The pinched hysteresis curves have been obtained without using analog multiplier for a wide range of frequency that varies from 600 kHz to 2 MHz. The property of retention has been verified for proposed design of memristor emulators after applying voltage pulse of amplitude 100 mV and frequency 1 MHz. Non-ideal analysis including the effects of parasitic impedances on the behaviour of proposed memristor emulators has also been presented. The proposed designs of memristor emulators have been simulated by Mentor Graphics Eldo simulation tool with TSMC 0.18 µm, level 53, CMOS technology parameters. The performance of proposed memristor emulator is verified by embedding it in the realization of current- mode analog filter. [ABSTRACT FROM AUTHOR]

The study presents two new realisations of bipolar two‐quadrant implicit RMS‐to‐DC converter and four‐quadrant multiplier/divider employing two VDTAs (voltage differential transconductance amplifier) and grounded passive elements. The converters provide the operating frequency of up to 10 MHz with increased precision in the processing of input currents signals, when compared to known realisations. Errors related to the signal processing and errors bound were investigated and presented in this study. The results obtained from the simulation tests in HSPICE and the experimentally realised models of the converters showed a good match with the theoretical anticipation. The maximum power consumption of the converters is 2.82 mW, at ±1.2 V supply voltages. [ABSTRACT FROM AUTHOR]

This paper presents the synthesis of fully deferential circuit that is capable of performing simultaneous high-pass, low-pass, and band-pass filtering in the log domain. The circuit utilizes modified Seevinck's integrators in the current mode. The transfer function describing the filter is first presented in the form of a canonical signal flow graph through applying Mason's gain formula. The resulting signal flow graph consists of summing points and pick-off points associated with current mode integrators within unity-gain negative feedback loops. The summing points and the pick-off points are then synthesized as simple nodes and current mirrors, respectively. A new fully differential current-mode integrator circuit is proposed to realize the integration operation. The proposed integrator uses grounded capacitors with no resistors and can be adjusted to work as either lossless or lossy integrator via tuneable current sources. The gain and the cutoff frequency of the integrator are adjustable via biasing currents. Detailed design and simulation results of an example of a 5th order filter circuit is presented. The proposed circuit can perform simultaneously 5th order low-pass filtering, 5th order high-pass filtering, and 4th order band-pass filtering. The simulation is performed using Pspice with practical Infineon BFP649 BJT model. Simulation results show good matching with the target. [ABSTRACT FROM AUTHOR]

This paper proposes a very simple analog control for quasi-square-wave zero voltage switching (QSW-ZVS) and triangular current mode bidirectional converters. The proposed circuit controls the inductance current, thanks to the use of a variable-width hysteretic current mode control. The upper and lower bounds of the hysteretic band are clamped to ensure QSW-ZVS operation with a single current command and independently from power flow direction. This enables the control to achieve a seamless transition between source and sink modes. The advantages and disadvantages of the proposed analog control are analyzed and two different power converters are built to demonstrate the validity of this solution: a 50 W, 48 to 24 V bidirectional buck converter and a 100 W, 24 to 48 V bidirectional boost converter. [ABSTRACT FROM AUTHOR]