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Smart material implication (SIMPLY) logic has been recently proposed for the design of energy-efficient Logic-in-Memory (LIM) architectures based on non-volatile resistive memory devices. The SIMPLY logic is enabled by adding a comparator to the conventional IMPLY scheme. This allows performing a preliminary READ operation and hence the SET operation only in the case it is actually required. This work explores the SIMPLY logic scheme using nanoscale spin-transfer torque magnetic tunnel junction (STT-MTJ) devices. The performance of the STT-MTJ based SIMPLY architecture is analyzed by varying the load resistor and applied voltages to implement both READ and SET operations, while also investigating the effect of temperature on circuit operation. Obtained results show an existing tradeoff between error rate and energy consumption, which can be effectively managed by properly setting the values of load resistor and applied voltages. In addition, our analysis proves that tracking the temperature dependence of the MTJ properties through a proportional to absolute temperature (PTAT) reference voltage at the input of the comparator is beneficial to mitigate the reliability degradation under temperature variations.

This paper investigates the impact of thermal stability relaxation in double-barrier magnetic tunnel junctions (DMTJs) for energy-efficient spin-transfer torque magnetic random access memories (STT-MRAMs) operating at the liquid nitrogen boiling point (77K). Our study is carried out through a macrospin-based Verilog-A compact model of DMTJ, along with a 65nm commercial process design kit (PDK) calibrated down to 77K under silicon measurements. Comprehensive bitcell-level electrical characterization is used to estimate the energy/latency per operation and leakage power at the memory architecture-level. As a main result of our analysis, we show that energy-efficient small-to-large embedded memories can be obtained by significantly relaxing the non-volatility requirement of DMTJ devices at room temperature (i.e., by reducing the cross-section area), while maintaining the typical 10-years retention time at cryogenic temperatures. This makes DMTJ-based STT-MRAM operating at 77K more energy-efficient than six-transistors static random-access memory (6T-SRAM) under both read and write accesses (-56% and -37% on average, respectively). Obtained results thus prove that DMTJ-based STT-MRAM with relaxed retention time is a promising alternative for the realization of reliable and energy-efficient embedded memories operating at cryogenic temperatures.

In this work we propose a channel backscattering model in which increased carrier temperature at the top of the potential energy barrier in the channel is taken into account. This model represents an extension of a previous model by the same authors which highlighted the importance of considering the partially ballistic transport between the source contact and the top of the potential energy barrier in the channel. The increase of carrier temperature is precisely due to energy dissipation between the source contact and the top of the barrier caused by the high saturation current. To support our discussion, accurate 2D full band Monte Carlo device simulations with quantum correction have been performed in double gate nMOSFETs for different geometries (gate length down to 10 nm), biases and lattice temperatures. Including the effective carrier temperature is especially important to properly treat the high inversion regime, where previous backscattering models usually fail.

In this paper we critically review and compare experimental methods, based on the Lundstrom model, to extract the channel backscattering ratio in nano MOSFETs. Basically two experimental methods are currently used, the most common of them is based on the measurement of the saturation drain current at different temperatures. We show that this method is affected by very poor assumptions and that the extracted backscattering ratio strongly underestimates its actual value posing particular attention to the backscattering actually extracted in nano devices. The second method is based on the direct measurement of the inversion charge by CV characteristics and gets closer to the physics of the backscattering model. We show, through measurements in high mobility p-germanium devices, how the temperature based method gives the same result of the CV based method once that its approximations are removed. Moreover we show that the CV based method uses a number of approximations which are partially inconsistent with the model. In particular we show, with the aid of 2D quantum corrected device simulations, that the value of the barrier lowering obtained through the CV based method is totally inconsistent with the barrier lowering used to correct the inversion charge and that the extracted saturation inversion charge is underestimated.

In this work we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in a one sub-band approximation and carrier degeneracy. The knowledge of the barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time we obtain also an estimate of the backscattering ratio and of the saturation inversion charge. Respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate length down to 70 nm. Moreover we propose an extension of the backscattering model to the case of 2D geometries (e.g. bulk MOSFETs). We found that, in this case, the backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1D approach can be significantly different from the real 2D value.

We propose a model for partially ballistic MOSFETs and for channel backscattering that is alternative to the well known Lundstrom model and is more accurate from the point of view of the actual energy distribution of carriers. The key point is that we do not use the concept of "virtual source". Our model differs from the Lundstrom model in two assumptions: i) the reflection coefficients from the top of the energy barrier to the drain and from top of the barrier to the source are approximately equal (whereas in the Lundstrom model the latter is zero), and ii) inelastic scattering is assumed through a ratio of the average velocity of forward-going carriers to that of backward-going carriers at the top of the barrier kv > 1 (=1 in the Lundstrom model). We support our assumptions with 2D full band Monte Carlo (MC) simulations including quantum corrections in nMOSFETs. We show that our model allows to extract from the electrical characteristics a backscattering coefficient very close to that obtained from the solution of the Boltzmann transport equation, whereas the Lundstrom model overestimates backscattering by up to 40%.

In this paper we show that through electrical characterization and detailed quantum simulations of the capacitance-voltage and current-voltage characteristics it is possible to extract a series of material parameters of alternative gate dielectrics. We have focused on HfO2 and HfSiXOYNZ gate stacks and have extracted information on the nature of localized states in the dielectric responsible for a trap-assisted tunneling current component and for the temperature behavior of the I-V characteristics. Simulations are based on a 1D Poisson-Schrdinger solver capable to provide the pure tunneling current and Trap Assisted Tunneling component. Energy and capture cross section of traps responsible for TAT current have been extracted., Comment: Preprint version of a paper submitted to TED, Transaction on Electron Devices. this is the final reviewed version. This work studies HfO2 and HfSiXOYNZ gate stacks, their C-V and I-V characteristics. A temperature dependent Trap Assisted Tunnneling model was developed to explain the temperature dependence of the I-V chaacteristics