Search

Recently, multilevel Resistive RAM (ReRAM) stacks have been demonstrated to have promising applications related to inference and learning in artificial intelligence. However, extensive studies on energy efficiency, repeatability, and retention during multilevel operations have not been undertaken previously. It is, therefore, required to investigate the device characteristics such as compliance current (CC) dependence, forming voltage, memory window, symmetry, and switching energy. Furthermore, understanding the impact of dielectric composition and/or electrode materials is necessary to optimize the device performance, such as switching characteristics, endurance, and energy efficiency. In this work, we have investigated a two-terminal ReRAM device, 10nm Ti/50nm TiN/7nm HfO2/1nm Al2O3/PVD Ti/TiN (Fig. 1), with bilayer switching dielectrics of HfO2 and Al2O3. In this case, the embedded Al2O3 layer was placed between the HfO2 layer and the top electrode (TE). We have evaluated the gradual resistance change capability with varying CC. The I-V characteristics of the ReRAM device, measured by a dc double sweep, is shown in Fig. 2. The device switched at a compliance current of 50nA with a forming voltage of 1.85 volts to set to low resistance state (LRS) from the high resistance state (HRS). The subsequent reset from LRS to HRS was obtained during the negative voltage ramp showing a bipolar switching operation (Fig. 2). With the variation of compliance current (50 nA to 70 nA), the LRS was gradually changed indicating multilevel LRS. It is known that by increasing the compliance current with a gradual set process, multiple conducting filaments (CFs) or thicker CFs can form setting the different LRS values and the annihilation of the CFs during the reset process can also moderately vary the HRS values. The resistance ratio between the HRS and LRS was observed to be more than 1000. The devices were subjected to 100 cycles of SET and RESET operations at different CCs without any failures. When the embedded Al2O3 layer was placed between the bottom electrode (BE) and the HfO2 layer, the switching compliance current was increased to 10 mA with a reduced forming voltage of 1.6V. Multilevel LRS states were observed for this device when the CC was varied from 10 mA to 12 mA for 100 cycles at each CCs. To further understand the behavior, TEM depth profile measurements were carried out, and it was observed that Al2O3 diffused from the peak at the as-deposited location into the HfO2 layer in both cases. While this improved the uniformity in switching behavior, the low switching energy consumption in the case of an embedded Al2O3 layer in between the HfO2 layer and the TE layer remains to be investigated. Replacing the PVD Ti layer (Fig. 1) with ALD Ti in the TE when an Al2O3 layer was between the bottom electrode (BE) and the HfO2 layer reduced the switching compliance current from 10 mA to 100 nA. This suggests that the metal quality of the TE can impact the switching behavior of the multilevel ReRAMs. Figure 1

Metal-insulator-metal (MIM) stacks, though simple in design, are the backbone device for resistive random access memories (ReRAM) and, as such, play a vital role in emerging memory technologies. In this work, we characterize the impact of Ar, Ar/N2, and BCl3/Cl2 plasma processes on the physical properties of the TiN bottom electrode (BE) surface. The BCl3/Cl2 process increases roughness by 40%. Ar and Ar/N2 processes both decrease PVD TiN roughness by 50%. This reduction propagates through the entire MIM stack. X-ray photoelectron spectroscopy (XPS) indicates that both plasma processes alter the Ti-ON concentration on the TiN surface. The impact of BE surface roughness and composition on MIM electrical properties is currently under investigation.

In this work, we presented the Hf-Zr system as a case study of materials that were evaluated in the past and are now receiving renewed interest due to its potential use in artificial intelligence (AI). A historical overview of Hf-Zr research and its promising new applications for emerging memories will be shared.

This paper investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks that were subjected to different slot plane antenna oxidation (SPAO) conditions: 1) prior to any high-k atomic layer deposition (ALD); 2) in between Al2O3 and ZrO2ALD layers; and 3) after the ALD of high- ${k}$ layers. The carrier transport mechanisms as a function of temperature on these samples were observed to be different. The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers depending on the SPAO treatments. Fowler-Nordheim tunneling seems to be the dominant transport mechanism at high field range when SPAO was performed after the high- ${k}$ layers were deposited. On the other hand, Poole-Frenkel emission and hopping conduction mechanism are dominant for other two samples in both gate electron injection and substrate electron injection (SEI) modes. The trap center ( $ {\phi }_{\text{t1}} = {0.13}$ eV) remains in the ZrO2 when ZrO2 is not subjected to the SPAO. Trap energy level $ {\phi }_{\text{t1}}$ (0.13 eV) was removed and $ {\phi }_{\text{t2}}$ (0.27 eV) still exists when only Al2O3 oxide layer was exposed to SPAO. Hopping distance, ${a}$ (about 0.3 nm) is extracted by hopping conduction model. After time dependent dielectric breakdown measurement, it was found that if GeO2 exists at the interface then it can be degraded easily by SEI stress. On the other hand, if SPAO was processed in between the high- ${k}$ layers the formation of a GeOx layer enhances the interface quality and provides better immunity to degradation under stress.

Historically, complementary metal-oxide-semiconductor (CMOS) technology was driven by geometrical scaling of the front-end-of-line (FEOL) transistor but it has slowed down significantly in recent years. On the other hand, back-end-of-line (BEOL) interconnects are projected to continue scaling aggressively to meet power, performance and area targets in advanced nodes. In this paper, we will introduce and review BEOL interconnect options targeting sub-7nm metal pitch with an emphasis on materials and process technologies.

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation. Reference Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014). S. Goley, M. K. Hudait, Materials, 2301 (2014). Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)

Neuromorphic computing represents a potential paradigm shift from conventional von Neumann computing architecture and shows promise for achieving massive parallelism and power efficiency for such data-centric tasks as image recognition and language processing. Based on the concept of synaptic plasticity, human-like machine learning can be potentially realized by use of arrays of electronic synapses that function in an analogous manner to biological neurons. One of the key features of this type of computing is the ability to control synaptic weights in an analog-like fashion for use in both inference and training applications. A number of existing device technologies in non-volatile memory systems exhibit attractive characteristics for such synaptic devices.[1,2] In particular, resistive switching devices (resistive random-access memory or ReRAM) can change and store their conductance value (G) in response to electrical stimuli making them potentially enabling for deep learning applications involving synaptic weights. For ReRAM devices, HfO2-based thin films can be utilized for filamentary oxide ReRAM and are an attractive option due to their fab-friendly processing and current implementation in high-volume manufacturing. In this study, we evaluated atomic layer deposition (ALD) for the growth of HfO2 for integration in both front-end-of-line (FEOL) and back-end-of-line (BEOL) compatible test structures on 300 mm wafers in order to optimize electrical performance for use as synaptic device elements in neuromorphic architectures. The effect of oxidant in the ALD process was evaluated and it was shown that H2O outperformed O3 in terms of better uniformity and lower forming voltage. By utilizing a hydrogen-based plasma either after the deposition or inserted as an intermediate step during deposition we were able to further decrease forming voltage for a fixed dielectric thickness. Reducing deposition temperature to 200°C in conjunction with the hydrogen-based plasma treatment offered an additional tuning knob to further reduce forming voltage. Stable high-resistance switching (> 100 kΩ) with analog behavior in scaled BEOL devices was also obtained using this optimized HfO2-based ReRAM. Additionally, a tight distribution of forming voltage was obtained ensuring that 99.9999% devices in a 14 nm ReRAM module can be formed below the targeted voltage. References Kuzum et al., Nanotechnology, 24, 382001 (2013) W. Burr et al., Advanced in Physics:X, 2, 89 (2016)

One of the key challenges for Ge gate stack is to achieve an improved interface quality between Ge and the high-K dielectric. In order to overcome this limitation, various interface treatments like ozone pre-gate treatment and ozone ambient annealing (1), nitridation of Ge surface (2),formation of a GeO2 layer between Ge and high-K dielectric using ECR plasma technique (3) and formation of an ultra-thin SiO2/GeO2bilayer have been tried. It has recently been reported that slot plane antenna(SPA) microwave plasma treatment helps to improve the EOT and enhances the oxide quality by reducing impurities and leakage current when the dielectric is exposed during or after deposition (4). Moreover SPA oxidation possesses the unique property of having low electron temperature, which makes it a very low damage process compared to other techniques,either inductively coupled plasma(ICP) and electron cyclotron resonance(ECR) plasma (5). In this study we investigated the impact of SPA plasma oxidation (SPAO) treatment in improving the interface quality when MOS capacitors were fabricated on 300mm p-type Ge substrates. SPAO plasma treatments were performed at different steps in the high-k deposition process. The substrate was initially subjected to a dry chemical oxide removal (COR) process. Subsequently, three different sets of samples were prepared with the exposure of SPAO plasma at following locations (Fig.1): CASE-1: SPAO plasma treatment after Al2O3(1nm)/ZrO2(3.5nm) deposition; CASE-2: SPAO plasma treatment was carried out in between Al2O3(1nm) and ZrO2(3.5nm) deposition; CASE-3: the Ge substrate was exposed to SPAO plasma treatment after COR and prior to Al2O3(1nm)/ ZrO2(3.5nm) layer deposition. Al2O3(1nm) and ZrO2(3.5nm) layers were deposited by atomic layer deposition. Capacitance-voltage at multi-frequencies,current-voltage and conductance measurements were performed at room temperature. Parameters like flatband voltage (Vfb), equivalent oxide thickness(EOT), interface state density(Dit),and leakage current were estimated accurately after quantum mechanical corrections and eliminating the series resistance effect. As shown in Fig. 2 lowest fast interface state density is achieved when SPAO plasma treatment was performed after Al2O3 and prior to ZrO2 deposition (CASE-2). A comparable Dit is also observed when plasma exposure was done after the entire gate stack deposition (CASE-1) (Fig.2). From different experimental results significant degradation to both the dielectric quality and interface was observed when SPAO is performed just after COR (CASE-3). References: 1) Zhao Mei et al, Journal of Semiconductors, Volume 34, No. 3, 2013. 2) A. Dimoulas et al, Appl. Phys. Lett., volume 86, no. 3, 2005. 3) Yukio Fukuda et al, IEEE transaction on electron devices, volume 57, No. 1, 2010. 4) M.N. Bhuyian et al, ECS Journal of Solid State Sci and Techn, vol. 3(5), N83, 2014. 5) C. Tian et al, J. Vac. Sci. Technol. A 24, 1421, 2006. Figure 1

Multi-patterning processes such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) present new challenges to the semiconductor device manufacturing such as increased relative cost to previous nodes, longer cycle times, and increased (local) edge placement error between grid and cut/block layers. As the scaling requirements continue, the factors driving both EPE and electrical yield such as overlay, critical dimension control (CDU) and stochastics (LCDU) become greater concerns to multi-patterning. In addition to lithographic process variations, the unit processes such as plasma/vapor etch, deposition, wet/cleans can contributes additional variation in spacer/mandrel profiles leading to poor CDU control and ultimately within-wafer pitch walking. In this paper, we outline alternative SAQP integration schemes to improve the feature profile of both mandrel and spacer to minimize process variability. This patterning scheme designated as fly-cut SAQP introduces new concepts such top spacer removal by chemical-mechanical planarization, mandrel foot mitigation layers, multi-layered mandrel for accurate polish end-point and void-free gap fill to realize high fidelity transfer to the underlying hardmask. Finally, we will demonstrate the effectiveness for this new integration scheme as a candidate for multi-color/self-aligned block (SAB) and highlight the additional benefits of using such an approach.

In this paper we present an overview and examples of thin films processing technologies for future generations of leading edge semiconductor devices. We introduce the main driving forces affecting future thin film deposition and etch technologies including the push for 3D (vertical) power, performance and area scaling. We discuss new thin films processes on the near term horizon that enable future devices, improved contacts, scaled 3D interconnects, and advanced patterning technologies followed by a future outlook for scaling.

For exploring the prospect of higher-k dielectric phase engineering on a high mobility substrate, films of Hf1-xZrxO2 with varying x-values (0 ≤ x ≤ 1) were deposited on Al2O3 passivated Ge substrates using atomic layer deposition (ALD) with a cyclic deposit-anneal-deposit-anneal (DADA) scheme. The evolution of monoclinic to higher-k tetragonal structure with increasing ZrO2 concentration was probed by grazing incident x-ray diffraction and partial reciprocal space maps using the highly brilliant synchrotron x-ray source at the Cornell High Energy Synchrotron Source (CHESS). A primarily amorphous/nano-crystalline matrix of the as-deposited films changed to randomly aligned grains of nanocry stalline MO2 (M=Hf, Zr) after post deposition annealing at 800 °C for 200 seconds. In contrast, the DADA films annealed for same thermal budget showed high degree of preferred orientation along certain crystallographic directions. With increasing ZrO2 content, the structure of the films changed from a monoclinic to a tetragonal phase. A lower amount of ZrO2 (x = 0.33) was required for stabilizing the tetragonal phase in films grown on Al2O3 passivated Ge substrate as compared to similar films grown on a Si substrate via the same DADA process (x ≥ 0.50).

Even through Ge/high-k interface has been extensively studied the high leakage current associated with these gate stacks continues to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). Since several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are important and bulk defect and interface defect concentration affect the CV and GV characteristics several corrections to the characteristics are required to obtain accurate values. We have measured the CV and GV characteristics of Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN MOS capacitors with three different interface treatments by HP4284 LCR meter using different frequencies. The interface treatments are (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). The plots were corrected by three different methods. Firstly, we removed the effect of sheet resistance, RS . The second approach uses data (capacitance and conductance) measured at two different frequencies to solve two unknown variables (capacitance and conductance) (1). The solved CV plot is closer to the corrected CV plot at 1 MHz rather than that at 100 KHz. This allows us to use 1MHz corrected data to obtain the EOT information. Additionally, this approach helps to verify that 1MHz data is robust assuming that defects do not respond to the other frequencies used here. The third approach is to modify the measurement circuits (2) to enhance CV and GV characteristics. Fig. 1 shows the CV characteristics after the corrections by three different approaches for three different samples. COR&SPAOx samples show excellent CV characteristics. The details of all the correction methods and the advantages of these methods to correct CV and GV will be discussed. We will demonstrate that the correction methods are suitable for accurately measure the interface characteristics. The Dit calculated by two method (conductance and capacitance spectroscopy) (Fig. 2) are compared and discrepancy of the results between different samples and different methods will be explained. References Y. Ding and D. Misra, J. Vac. Sci. Technol. B, 33, 021203, 2015. K.J. Yang and C. Hu, IEEE Trans on Electron Dev, 46(7), 1500, 1999. K.S.K Kwa, S. Chattopadhyay, N.D. Jankovic, S.H. Olsen, L.S. Driscoll, and A.G. O'Neill, Semicond. Sci. Technol., 18(2), 82, 2003. Figure 1

As Si metal oxide semiconducting field effect transistors have continued to scale, SiO2-based gate dielectric and polySi gates have been successfully replaced by high-k dielectrics and metal gate at the 45nm technology node and beyond. In order to continue scaling, improvements of key film properties of the high-k dielectric, such as k-value and leakage current, are needed. The electrical properties of HfO2-based dielectrics may be enhanced by structural modifications, since the k-value is dependent on the crystalline phase (monoclinic k=16, tetragonal k=70 and cubic =29) [1]. HfO2 films typically crystallize into the monoclinic phase, which is its most thermodynamically stable phase [2,3]. Alloying HfO2 with other oxides such as ZrO2, TiO2, Al2O3offer a viable option towards engineering the crystalline phase. In this regards, we have deposited 40 cycles of Hf1-xAlxOy films by atomic layer deposition with Al/(Hf+Al)% ranging from 0 to 25%. A set of samples were annealed under N2 at temperatures ranging from 680 oC to 800oC and compared to the as deposited samples. To investigate the crystallinity of the films, we performed grazing incidence in-plane X-ray diffraction (GIIXRD) on the annealed films and in-situ XRD during an anneal process using synchrotron radiation was used to determine the crystallization temperature (Tc) for the unannealed films. The GIIXRD measurements revealed the presence of non-monoclinic peaks which was also confirmed by the in-situ anneal XRD measurements. The crystallization temperature of the non-monoclinic phase obtained from the in-situ anneal XRD is plotted in Fig.1, where it is shown that higher Al/(Hf+Al)% results in higher Tc. In order to resolve the non-monoclinic phase, extended X-ray absorption fine structure (EXAFS) at was utilized. The EXAFS measurement combined with GIIXRD showed the ALD Hf1-xAlxOy films crystallize into a mixture of the tetragonal and monoclinic phases. The electrical properties were investigated by MOS capacitors with ALD TiN as the metal gate. The electrical measurements show a reduction in EOT after post deposition anneal (PDA). In addition, the leakage current was also reduced by a factor of 10 while maintaining a flat-band voltage that is comparable to PDA HfO2 films under identical conditions. The C-V plots of the as deposited samples and annealed samples are shown in Fig. 2 and Fig.3 respectively. We also investigated the effect of different thermal budgets on the Hf1-xAlxOy films. A ~2Å EOT reduction with lower gate leakage was obtained for devices with post deposition anneal near the crystallization temperature of the Hf1-xAlxOyfilms. However, the electrical performance is degraded for devices with higher or lower post deposition anneal temperature than the films’ crystallization. In summary, we have successfully deposited ALD Hf1-xAlxOy. The crystal phase was confirmed to be a mixed phase of tetragonal with monoclinic. The data shows an enhancement in electrical properties near the crystallization temperature of the Hf1-xAlxOyfilms. Acknowledgements Diffraction measurements were carried out at NSLS (X20A and X20C), BNL, which is supported by the DOE, Division of Materials Sciences and Division of Chemical Sciences, under Contract No. DE-AC02-98CH10886. References [1] X. Zhao et al., Phys. Rev. B, 65, 233106 (2002). [2] E.P Gusev, V. Narayanan, M. M Frank, Phys. Status Solidi A, 201, 1443 (2004). [3] D. A Neumayer, E. Cartier, J. Appl. Phys., 90, 1801 (2001).

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10). In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices. The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004). Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007). M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002). B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000). L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002). W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Use of Hf based high-k dielectric materials enabled CMOS device scaling beyond the 22 nm technology node. In order to scale the equivalent oxide thickness (EOT) to 0.7 nm and beyond, while achieving good reliability performance, improvement of the film properties and the deposition methods are highly desirable. It was observed that, the dielectric constant of ALD HfO2 can be improved by the addition of ZrO2 as it offers higher-k tetragonal stabilization when Zr/(Hf+Zr) percentage is more than 50% (1-2). It has recently been reported that the poor dielectric characteristics of ALD grown oxide films, such as the leakage current, can be improved by exposing the dielectric films to a slot-plane-antenna (SPA) plasma (3). Because of low electron temperature the SPA process causes very little damage as compared to conventional inductively coupled plasma (ICP) or electron cyclotron resonance (ECR) plasma (4). Also cyclic treatment during the ALD deposition process by using room temperature ultraviolet ozone, D2O radical, remote microwave N2O plasma, and/or thermal annealing have shown promising results toward improving film properties (5-7). In this study, for the first time, we examined the performance benefits due to the use of intermediate SPA Ar plasma treatment (DSDS) in the ALD deposition process of Hf1-xZrxO2 with 0%, 31% and 80% Zr/(Hf+Zr) percentages and compared them with the standard deposition process (As_Dep). Zr percentage was varied by precisely controlling the Hf-precursor to Zr-precursor pulse ratio in the ALD cycle. MOSCAPs were formed with TiN as gate material, where ALD Hf1-xZrxO2 was deposited on a SiON interface formed by remote plasma radical flow nitridation of chemically grown oxide on a p-Si substrate. It is observed that, DSDS Hf1-xZrxO2with 80% Zr has the lowest dielectric thickness and interfacial layer thickness as compared to others (Fig. 1(a)). Equivalent oxide thickness (EOT) for different Zr percentages for DSDS and As-Dep processing conditions were also compared. Effect of SPA Ar plasma and Zr addition on the reliability of ALD Hf1-xZrxO2 were monitored from the flat-band voltage shift due to a constant field stress at E= 27.5 MV/cm in the gate injection mode (Fig. 1(b)). Also, the gate leakage current density, before and after stress for different devices were monitored. When subjected to a constant field stress traps are generated in the gate dielectric and at the Si-IL interface. DSDS Hf1-xZrxO2with 80% Zr showed the lowest initial flat-band voltage shift after the first 20-second stress and the subsequent increase of positive charge formation was observed as the stress continued. Devices with intermediate Ar plasma have reduced gate leakage current density before stress and after 1000s stress, which implies suppression of oxide trap formation due to plasma exposure. Intermediate Ar plasma exposure to ALD Hf1-xZrxO2with 80% Zr seems to deposit superior dielectric with better EOT downscaling ability and good reliability performance. While Zr addition helps to produce a fine grain microstructure with less oxygen vacancies (2), SPA plasma further helps by reducing contaminants, increasing mass density, and superior bond structure of the film (3). References 1. K. Tapily et al,ECS Trans., 45 (3) 411-420 (2012). 2. R.I. Hegde, et al, J. Appl. Phys. 101, 074113 (2007) 3. T. Tanimura et al, J. Appl., Phys., 113, 064102 (2013) 4. C. Tian et al, J. Vac. Sci. Technol. A 24(4), 1421(2006). 5. S. Consiglio et al, ECS Trans., 41, 89 (2011). 6. R.D. Clark et al, ECS Trans., 35(4), 815 (2011). 7. A. Delabie et al, J. Electrochem. Soc.,153, F180 (2006). Figure 1(a): Dielectric thickness (filled symbols in the left scale) for DSDS and As-Dep gate oxides and interfacial layer (IL) thickness (open symbols in the right scale) for MOSCAPs with DSDS and As-Deposited HfO2 (0% Zr), Hf1-xZrxO2 (31% Zr), and Hf1-xZrxO2 (80% Zr). (All processes used 44 ALD cycles of HfO2/Hf1-xZrxO2 deposition at 2500 C) Figure 1(b): Flat-band voltage values obtained from Capacitance-Voltage (CV) characteristics for unstressed devices (filled symbols) and after 1000s stress (open symbols) with a constant field stress at E= 27.5 MV/cm in the gate injection mode. (MOSCAPS having HfO2 (0% Zr) are denoted by squares, Hf1-xZrxO2 (31% Zr) are denoted by circles, and Hf1-xZrxO2(80% Zr) are denoted by triangles.)

Resistive random-access memory (RRAM) device has attracted wide attention for next-generation nonvolatile memory (NVM) application due to simple structure, high cycling endurance, good retention, low power consumption and fast switching time (1, 2). In recent years, RRAM devices are extensively researched for multi-level data storage (3, 4). RRAM devices can be driven to various resistance states by applying suitable compliance current values during the switching operation. In this work, multilevel resistive switching behaviors of RRAM devices with three different dielectric materials like HfO2, HfAlO2 and HfZrO2 are investigated with fixed top/bottom electrodes. To control the resistance state, a thin Al2O3 layer (1 nm) was inserted between the bottom electrode and switching dielectric (Ti/TiN/Al2O3/HfAlO2 or HfZrO2 or HfO2/Ti/TiN). The fabrication details of these devices are presented elasewhere (5). Fig. 1 shows DC endurance cycling on the LRS/HRS resistances of the three RRAM structures, (a) HfAlO2, (b) HfZrO2 and (c) HfO2 for different increasing compliance currents. The endurance cycling is performed with 20 cycles per compliance level. As can be seen from the figure, different low resistance states (LRS) and high resistance states (HRS) are well resolved after dc endurance cycling for HfAlO2 and HfZrO2 based RRAM devices. Devices with HfO2, on the other hand, does not show any multilevel LRS or HRS behavior for increase in compliance current. The reason is possibly due to the lack of oxygen vacancies available in the HfO2-RRAM structure. When HfZrO2 was subjected to a post deposition annealing (PDA) in nitrogen environment, the resistance distribution of LRS and HRS was improved, possibly due to improvement of dielectric quality while the oxygen vacancy concentration remained the same. To further improve the resistance window an additional 2 nm thick TiN layer was added before the Ti layer on top electrode of HfZrO2 based RRAM. The cycle to cycle distribution of HRS/LRS resistance of HfZrO2 based RRAM was significantly improved while the compliance current for switching was increased. In summary, process optimization and electrode selection with HfZrO2 as the switching layer can provide significant multilevel storage in RRAM devices. References: E. Ambrosi, A. Bricalli, M. Laudato and D. Ielmini, Faraday discussions DOI: 10.1039/c8fd00106e (2018). A. Prakash and H. Hwang. Physical Sciences Reviews, vol. 1(6), (2016) Chen, et al., Semiconductor Science and Technology7 (2015): 075002. J. Jang and V. Subramanian. Thin Solid Films 625 (2017): 87-92. D. Misra, S. Sultana, B. Jain, N. Bhat, K. Tapily, R.D. Clark, S. Consiglio, C.S. Wajda, and G.J. Leusink, ECS Trans., vol. 86(2), 77, 2018. Figure 1

We have integrated ALD barrier and Ru liner for novel interconnect integration and have evaluated electrical properties and time dependent dielectric breakdown (TDDB). RC and via resistance were reduced by the ALD barrier, and particularly it was confirmed that TDDB performance can be improved by using ALD TaAlN with an ultrathin film. Accordingly, ALD TaAlN barrier and CVD Ru liner are attractive barrier/liner combination for next generation interconnect integration schemes.

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

Non-volatile resistive random-access memory (RRAM) devices are currently being investigated as a low power, high density and high-speed alternative DRAM (1). A transition metal oxide dielectric layer is typically used as an insulating layer in a metal-insulator-metal (MIM) structure. To reduce the large variability of switching parameters and high operation current in these RRAM devices, bilayer dielectric structures are being explored. In this work we have used several different bilayer structures using different dielectrics. In each device the bottom electrode (BE) was 10nm Ti/50nmTiN followed by 1nm Al2O3. The second dielectric layer or the switching layer was a 7-nm HfO2 (R3), HfZrO2 (R4 with Hf:Zr%=50%) or HfAlO2 (R1 with Hf:Al%= 3%) followed by the top electrode (TE) constituting of 8nm Ti/6nm ALD TiN+50nm PVD TiN. In some cases, the top electrode was varied to 2nm ALD TiN/8nm Ti/6nm ALD TiN+50nm PVD TiN (R5) by adding a 2nm ALD TiN layer prior to 8nm Ti. Some devices with HfZrO2 (R2) were subjected to a post deposition anneal (PDA) at 700oC for 60 s. In all cases, to enhance the switching characteristics on the top electrode 8 nm Ti was used as the cap layer material except in the case of R5 where 2nm of ALD TiN was deposited prior to 8 nm of Ti. The use of thin dielectric layer of 1nm Al2O3 was to suppress the sneak-path problem (3) in the low resistance state (RON). Comparing the variation of switching layer, it was observed that the device with 1nm Al2O3/7nm HfAlO2 (R1) provided the superior average Roff/Ron values and both set and reset power compared to HfO2 (R3), and HfZrO2 (R4) devices. When the HfZrO2 (R4) devices were compared with the identical device with PDA (R2) Ron increased and Roff decreased for the PDA device, reducing the Roff/Ron value. Variation of cap layer to TiN instead of Ti also showed similar Roff/Ronbehavior. D. Ielmini, Semicond. Sci. Technol. Vol. 31, 063002, 2016. Xiaorong Chen and Jie Feng, Appl. Phys. A, vol. 120, 67 2015 U. Chand, K-C. Huang, C-Y. Huang, and T-Y. Tseng, IEEE Trans. on Electron Devices, vol. 62(11), 3665, 2015

The continued scaling of MOSFET devices necessitates the scaling of the gate dielectric in terms of equivalent oxide thickness (EOT) and associated k-value. As a replacement for SiO2 based gate dielectrics, which have reached their fundamental scaling limit, Hf-based dielectrics including HfO2, Hf silicate and nitrided Hf silicate have been chosen as viable materials.[1] Though the HfO2-based materials have generally been preferred, recent studies have shown that HfO2 with an admixture of ZrO2, which are both fully miscible, has the potential to provide a higher dielectric constant by means of stabilization of higher-k phases.[2,3] Moreover, the mixed oxide HfxZr1-xO2 has been shown to exhibit improved device performance and reliability compared to HfO2.[4] For the deposition of ultra-thin high-k gate dielectric films on planar structures, chemical vapor deposition may offer advantages in terms of wafer throughput, manufacturability, cost of ownership, and process flexibility compared to the alternately pursued atomic layer deposition based approaches. In this study we investigated the process characteristics and film properties of HfZrO4 (HfO2:ZrO2=1) thin films deposited using metallorganic chemical vapor deposition on a 300 mm production-worthy deposition chamber. The mixed oxide films were deposited using a mixture of Hf-t-butoxide and Zr-t-butoxide (1:1 molar ratio) at a wafer temperature of either 380°C or 480°C using O2 as a co-reactant. The Si wafers had a thin (~8A) layer of chemically grown SiO2. The physical properties of the films were analyzed using various characterization techniques including spectroscopic ellipsometry, corona-oxide-semiconductor (Quantox) leakage measurements, XRR, angle-resolved XPS, RBS, ICP-AES, and TEM. MOS capacitor structures featuring HfZrO4 dielectric were fabricated and tested using C-V and I-V measurements. Key electrical parameters (EOT, leakage current density, VFB) were compared with structures featuring HfO2 deposited using the same deposition system and process conditions used for the HfZrO4 process. The HfZrO4 growth rate (Fig.1) was observed to be the same for both deposition temperatures, thus indicating a mass transport limited growth rate regime. Density was observed to increase with deposition temperature in line with reported values for ALD-deposited HfZrO4 from metal chloride sources.[3] The increase in film density (and possibly decrease in film impurities) is also corroborated by improved Quantox measured leakage (Fig.2) as well as increase in metal coverage rates (Fig.3). Improvements in Jg vs EOT trends were observed when comparing HfZrO4 with HfO2 in MOS capacitor structures. Additionally, no measurable difference in CV hysteresis was observed for HfZrO4 compared to HfO2. In our deposition system an excellent wafer-to-wafer repeatability (0.86%) was observed for a mean thickness of 19 A over a 50 wafer run. These results indicate that MOCVD HfZrO4 is a promising material for advanced high-k applications. Figure 1. XRR measured thickness values and densities for HfZrO4 films deposited at 380°C and 480°C and associated growth rates determined from linear fits.

In this paper we will review some of our previous work on ALD deposited high-K dielectric stacks as well as present some of our more recent advances. We have shown that ALD can be used successfully to deposit high quality high-K gate dielectrics of Hf and Zr oxide. In addition, because of the inherent conformality of ALD processes, these dielectrics can be easily migrated to advanced device structures such as FINFETs. We have also been successful in developing ALD processes to deposit rare earth oxides (REOs), such as Y2O3 and La2O3. These processes are useful in creating layered dielectric structures where the REO functions as a threshold voltage adjustment layer. We use physical and electrical characterization of the films as deposited by ALD, including spectroscopic ellipsometry, corona oxide semiconductor charge measurement, TXRF, AES, angle resolved XPS, HRTEM, AFM, MEIS, and RBS, to provide information on the film growth mechanism and the primary parameters that influence the ALD growth of high-K oxides. We further correlate these findings with basic electrical results obtained from MOSFET and MOSCAP devices fabricated using our ALD processes to understand how process changes affect both the as-deposited films as well as the resulting devices.

Material interactions in advanced high-κ / metal gate stacks can have a significant effect of the performance of completed devices. The effect of these interactions was investigated using planar MOS capacitor stacks that might be used for the gate of a MOS transistor. Gate electrode materials included TaN, TaSiN, and W, and HfSiO and HfSiON were used as the gate dielectric materials with an ultra-thin SiO2 interface between the silicon substrate and the dielectric. Deposition methods included CVD and ALD.

Resistance capacitance time delay in Cu interconnects is becoming a significant factor requiring further performance improvements in future nanoelectronic devices. Choice of alternate interconnect materials, for example, refractory metals, and subsequent integration with underlying barrier and liner layers are extremely challenging for the sub-10 nm nodes. The development of conformal deposition processes for alternate interconnects, liner, and barrier materials are crucial in order for implementation of a possible replacement for Cu interconnects for narrow line widths. In this study, the authors report on ultrathin (∼3 nm) chemical vapor deposition (CVD) grown ruthenium films on 0.5 and 1 nm thick metal nitride (TiN, TaN) barrier layers deposited via atomic layer deposition (ALD). Using scanning electron microscopy, the authors determined the effect of the underlying barrier layer on the coverage of the ruthenium overlayer. The authors utilized synchrotron x-ray diffraction with in situ rapid thermal an...

In this paper, we provide a mechanistic understanding of mobility degradation of gate-last ZrO 2 subjected to medium thermal budget annealing. We find that high-k post deposition anneal (PDA) even at modest temperatures can improve the interfacial layer (IL) and bulk oxide, but mobility suffers. The mechanism for this mobility degradation is the enhanced remote Coulomb scattering from nonstoichiometric ZrO x region near the IL. The high-k PDA, even at moderate temperature, enables oxygen gettering of the IL and deprives oxygen from ZrO 2 near the IL, which results in the accumulation of defects/traps in the region near ZrO 2 /IL interface. This enhances remote Coulomb scattering due to the high concentration of oxide traps and their close proximity to the conductance channel. Consequently, mobility is degraded even though IL and bulk oxide are improved.

Using a five-step atomic layer deposition (ALD)-anneal (DADA) process, with 20 ALD cycles of metalorganic precursors followed by 40 s of rapid thermal annealing at 1073 K, we have developed highly crystalline Hf1−xZrxO2 (0 ≤ x ≤ 1) thin films (

As device feature sizes have continued to scale, new device engineering and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations in reducing short channel effects and improved performance are through the introduction of FinFETs, nanowires, and high mobility channel materials. High mobility channel materials, such as Ge and III-V (InGaAs, GaAs), are attracting increasing interest due to the possibility of realizing increased performance even without scaling the gate length of the device (1-3). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing compatibility. In this paper we report progress in high-k phase engineering through HfO2:ZrO2 doping combined with intermittent annealing and post deposition microwave plasma oxidation in order to achieve sub nm EOT with reasonable leakage. In this regard, 300mm epi Ge/Al2O3/ZrO2/TiN MOSCAP devices were fabricated using epitaxially grown Ge. We have utilized a TEL CertasTM Chemical Oxide Removal (COR) process (4), which uses anhydrous HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. The high-k stack Al2O3/HfxZr1-xO2 were deposited by atomic layer deposition on a TEL Triase +TM tool. The ALD HfxZr1-xO2 films were deposited using a cyclical deposition and annealing scheme (termed DADA) (5-6). Prior to the ALD HfxZr1-xO2 a thin ALD Al2O3 was deposited. An additional post microwave plasma oxidation was also carried out in situ. A post plasma Al2O3/ZrO2control sample with no DADA process was also fabricated. Figure 1 shows electrical leakage Jg vs equivalent oxide thickness (EOT). The electrical analysis show a scaled EOT of ~0.6nm with the combination of DADA and post plasma oxidation compared to the control sample with only post plasma oxidation processed, see Fig.1. In addition, DADA processed samples without additional post plasma oxidation (6) resulted in very high leakage. The impact of post plasma oxidation and DADA on the electrical and physical characteristics of the Hf based dielectrics will be discussed in detail. References 1.S. Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). 2.L. Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). 3. C.H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014) 4.T. Sugawara, S. Matsuyama, M. Sasaki, T. Nakanishi, S. Murakawa, J. Katsuki, S. Ozaki, Y. Tada, T. Ohta, N. Yamamoto, Jpn. J. Appl. Phys., 44, 1232 (2005). 5. K.Tapily, S. Consiglio, R.D Clark, R. Vasic, E. Bersch, J. Jordan-Sweet, I. Wells, G. Leusink, ECS Trans. 45, 411 (2012). 6. Sonal Dey, Kandabara Tapily, Steven Consiglio, Kai-Hung Yu, Robert D. Clark, Cory S. Wajda, Gert J. Leusink, Arthur R. Woll and Alain C. Diebold (2016). Higher k Tetragonal Phase Stabilization in Atomic Layer Deposited Hf1-xZrxO2 (0 Figure 1

Over the past decade traditional scaling by simple linear shrinking has effectively ceased as IC makers have adopted new 3-dimensional device structures, complex integration schemes and new processes and materials for an expanding number of applications in order to overcome fundamental physical limits. This trend will accelerate as devices are scaled to a level approaching atomic dimensions. Dielectric materials with tailored properties are required to meet future device needs. And deposition processes that are self-limited (e.g. Atomic Layer Deposition (ALD)), or self-directed (e.g. selective deposition) will enable those materials to be used in scaled 3D devices. Highly tailored ALD processes are being investigated to fabricate functional material layers. Interspersed treatments and doping to make ternary materials may be used to modify the physical and electrical properties of ALD films further in order to optimize the resulting physical or electrical properties. To improve device contacts, ultra-thin dielectrics and metal layers may be deposited inside of high aspect ratio contact structures in order to provide lower contact resistivity- or may be used to provide solutions for integration of new contact structures. Selective deposition processes can be used to deposit functional materials only where they are needed, thus reducing the patterning burden during IC manufacturing. Future use of new transistor channel materials, such as III-V and Ge, will require the use of ALD gate dielectrics with compatible treatment schemes in order to passivate defects and provide EOT scaling inside of ultra-high ratio replacement gate structures. Examples of these and similar processes will be described and discussed with the goal of discerning a path beyond 10nm devices.

In this study, the authors investigated atomic layer deposition (ALD) of B2O3 and BN for conformal, ultrashallow B doping applications and compared the effect of dopant-containing overlayers on sheet resistance (Rs) and B profiles for both types of films subjected to a drive-in thermal anneal. For the deposition of B2O3, tris(dimethylamido)borane and O3 were used as coreactants and for the deposition of BN, BCl3 and NH3 were used as coreactants. Due to the extreme air instability of B2O3 films, physical analysis was performed on B2O3 films, which were capped in-situ with ∼30 A ALD grown Al2O3 layers. For the BN films, in-situ ALD grown Si3N4 capping layers (∼30 A) were used for comparison. From spectroscopic ellipsometry, a thickness decrease was observed after 1000 °C, 30 s anneal for the B2O3 containing stack with 60 ALD cycles of B2O3, whereas the BN containing stacks showed negligible thickness decrease after the annealing step, regardless of the number of BN cycles tested. The postanneal reduction in...

This work investigates the interface state density, Dit by conductance method for two different processing conditions: (1) cyclic deposition and slot-plane-antenna (SPA) Ar plasma exposure, DSDS, and (2) cyclic deposition and annealing, DADA, during the deposition of ALD Hf1-xZrxO2 to fabricate the TiN/Hf1-xZrxO2/SiON/Si gate stack. The Zr percentage was varied in the dielectrics from x = 0 to 0.31 and 0.8 for DSDS processing and x = 0 to 0.8 for DADA processing. The control samples were deposited with standard atomic layer deposition (ALD) process (As-Dep) without any cyclic treatment. The addition of ZrO2 and SPA plasma exposure is found to suppress interface state generation. DSDS Hf1-xZrxO2 with x = 0.8 demonstrated superior equivalent oxide thickness downscaling and the lowest Dit. The electron affinity variation of Hf and Zr ion seems to contribute to reduced Dit generation after a constant voltage stress. On the other hand, DADA process increases the midgap Dit when Zr is added to HfO2. In addition...

The continuous scaling of Cu interconnects for sub-10nm technology nodes calls for development of ultrathin and conformal Cu diffusion barriers. Due to its ability to conformally deposit films with nanoscale thickness control, atomic layer deposition (ALD) is an attractive method for depositing refractory metal nitride diffusion barrier layers, as opposed to a line-of-sight technique such as physical vapor deposition (PVD).[1] In this regard we have previously demonstrated extendability of Cu fill (with Ru seed layer) below 25 nm linewidth (200 nm height) when PVD TaN is replaced with ALD TaN.[2] In 40 nm Cu dual damascene structures with 3 nm barrier layers, ALD TaN has also been shown to reduce via resistance by ~28% compared to PVD TaN in spite of 20x lower blanket resistivity for PVD TaN.[3] In order to further improve ALD grown TaN and minimize Cu-diffusion through these ultrathin barrier films, it is desirable to avoid forming polycrystalline films with inherent grain boundary diffusion pathways. Accordingly, alloying refractory transition metal nitrides with a third element (as for example Al) may offer a promising method for maintaining metastable amorphous films by interrupting the typical polycrystalline phase formation.[4,5] In this study, ultrathin TaN and ternary Ta1-xAlxNy films (denoted TaAlN) were deposited by ALD using metallorganic precursors and were evaluated for their effectiveness in Cu diffusion barrier applications compared to a PVD grown TaN control. TaN was deposited using tert-butylimido tris(ethylmethylamido)tantalum (TBTEMT, Ta(NCMe3)(NEtMe)3) and NH3 at 350 °C with a growth per cycle (GPC) of ~ 0.7 Å/cycle. ALD TaAlN ternary alloy films were deposited by addition of trimethylaluminum/NH3 cycles to the TBTEMT/NH3cycles using Ta:Al cycle ratios in the range 16:1 to 2:1, resulting in Al/(Al+Ta)% in the range of 21% to 88%. The effectiveness of the barrier layers against Cu-diffusion in advanced interconnects were investigated using in-situ ramp anneal synchrotron x-ray diffraction (XRD) [6,7] to study the effect of annealing on Cu diffusion with the presence of these ultrathin (~1.8 nm) barrier layers interposed between 50 nm PVD grown Cu and the Si substrate. The barrier failure temperature (Tc) was determined based on the onset of Cu3Si XRD peaks during the in-situ ramp anneal. The kinetics of Cu3Si formation was assessed by XRD using multiple ramp anneal rates and performing a Kissinger-like analysis [6] to determine the effective activation energy (Ea) for silicidation in presence of the Cu diffusion barrier layers. Compared to the film stack with PVD TaN barrier, the stacks with ALD TaN and TaAlN (Ta:Al = 8:1) exhibit a slightly higher Tc for Cu silicidation. The effective activation energy of Cu3Si formation for stacks with ALD TaN (Ea ~ 1.5 eV) and TaAlN (Ea ~ 1.3 eV) are close to the reported value for grain boundary diffusion of Cu (1.3 eV) [8], whereas the Cu3Si effective activation energy for the stack with PVD TaN (Ea ~ 2.3 eV) is closer to the reported value for lattice diffusion (2.7 eV).[8] Although the temperature of Cu3Si crystallization and corresponding barrier failure temperature is higher for these ALD barrier films compared to the PVD barrier TaN film, the failure mechanism for the ALD barriers is most likely dominated by grain boundary diffusion whereas the initial failure mechanism for the PVD barrier may be dominated by lattice diffusion. References [1] H. Kim, S-H. Kim, and H.-B.-R. Lee, Atomic Layer Deposition for Semiconductors, C. S. Hwang. Ed.; Springer, New York, 2014; pp. 209-210. [2] K. Yu, T. Hasegawa, M. Oie, F. Amano, S. Consiglio, C. Wajda, K. Maekawa, and G. Leusink, Proceedings of 2014 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 117 (2014). [3] O. van der Straten, X. Zhang, K. Motoyama, C. Penny, J. Maniscalco, and S. Knupp, ECS Trans., 64(9), 117 (2014). [4] M.-A. Nicolet, Appl. Surf. Sci., 91, 269 (1995). [5] M.-A. Nicolet and P.H. Giauque, Micro. Eng., 55, 357 (2001). [6] W. Knaepen, C. Detavernier, R.L. Van Meirhaeghe, J. Jordan Sweet, and C. Lavoie, Thin Solid Films, 516, 4946 (2008). [7] G. Rampelberg, K. Devloo-Casier, D. Deduytsche, M. Schaekers, N. Blasco, and C. Detavernier, App. Phys. Lett., 102, 111910 (2013). [8] T. Oku, E. Kawakami, M. Uekubo, K. Takahiro, S. Yamaguchi, and M. Murakami, Appl. Surf. Sci., 99, 265 (1996). Figure 1

As Si Metal Oxide Semiconducting Field Effect Transistors (MOSFETs) have continued to scale Short Channel Effects (SCE) have become exacerbated by the inability to continue scaling the Equivalent Oxide Thickness (EOT) of the device significantly beyond what was realized with the introduction of High K Metal Gate (HKMG) MOSFETs at the 45nm technology node. Since EOT scaling has not kept pace with the gate length (Lg) scaling needed to continually increase the transistor drive current, device makers have instead elected to introduce FinFET and Tri-Gate transistors with inherently better electrostatic control in order to realize reasonable SCE in the device. High mobility channel materials, such as Ge, are attracting increasing interest due to the possibility of realizing increased performance even without scaling the Lg of the device (1). Ge is particularly attractive for use as a channel material for P-type MOSFETs (PMOSFETs) due to its high hole mobility and Si processing compatibility. In fact, we have demonstrated experimental PMOSFET devices with hole mobilities significantly higher than what can be obtained on Si, Fig. 1. However, a significant remaining challenge to incorporating Ge into VLSI production is obtaining a stable and well-passivated dielectric/semiconductor interface using tooling and substrates compatible with current 300mm Si VLSI High Volume Manufacturing (HVM) in order to achieve reasonable device performance at sub 1nm EOTs (2). In this paper we will report progress on surface passivation and functionalization of Ge channel surfaces, as well as High K dielectric layer growth by Atomic Layer Deposition (ALD) and the resulting electrical properties measured by fabricated MOSFETs and Metal Oxide Semiconducting Capacitors (MOSCAPs). The Ge channel devices were formed on 300 mm Si wafers using Ge grown by an epitaxial process including a graded SiGe buffer layer. We have utilized a TEL CertasTMChemical Oxide Removal (COR) process (3), which uses dry HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. We have also studied Ge oxide interface layer formation by plasma oxidation using a Slot Plane Array (SPA) antenna (4) utilizing in-line X-ray Photoelectron Spectroscopy (XPS) to measure Ge and high K oxide thickness on monitor wafers fashioned by the same Ge epitaxial process used to make the electrical devices and compared it to the equivalent Si oxidation process, Fig. 2. Various other passivation and interface schemes were investigated and will be discussed, contrasted and compared including ozone oxidation, Al oxide passivation/interface layers, SPA plasma nitridation, and thin amorphous Si passivation layers. We have utilized Hf oxide grown by a previously reported ALD process (5) as the High K dielectric for our devices, and TiN as the metal gate. Our results show that Ge channel devices can be fabricated on 300mm Si substrates using Si VLSI-compatible toolsets and infrastructure and resulting in reasonable device characteristics, Fig. 3. Thus, Ge channel MOSFETs are found to be a promising technology for use in HVM at future VLSI technology nodes. References 1. S. Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). 2. L. Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). 3. T. Hamelin, J. Wallace, and A. LaFlamme, U.S. Patent No. 7029536. 4. T. Sugawara, S. Matsuyama, M. Sasaki, T. Nakanishi, S. Murakawa, J. Katsuki, S. Ozaki, Y. Tada, T. Ohta, N. Yamamoto, Jpn. J. Appl. Phys., 44, 1232 (2005). 5. R.D. Clark, S. Consiglio, C. Wajda, G. Leusink, T. Sugawara, H. Nakabayashi, H. Jagannathan, L.F. Edge, P. Jamison, V. Paruchuri, R. Iijima, M. Takayanagi, B. Linder, J. Bruley, M. Copel, V. Narayanan, ECS Trans. 16, 4, 291 (2008)

The reliability of atomic layer deposited Hf1-xZrxO2 with x=0.8 on a SiON interfacial layer (IL) has been analyzed in detail for three different oxide deposition processes, (i) DADA: samples were subjected to dielectric deposition and thermal annealing in a cyclical process; (ii) DSDS: samples were subjected to similar cyclical process with dielectric deposition and exposure to Ar plasma; and (iii) As-Dep: the dielectric for the control samples was deposited without any intermediate step. Capacitance-voltage and current-voltage characteristics of the MOS capacitors (MOSCAP) with metal gate (TiN), subjected to a constant field stress of 2.75 × 107 V/cm in the gate injection mode, show that the flat-band voltage shift (∆VFB ) and stress induced leakage current (SILC) below 100 s stress is the lowest for DSDS samples whereas the worst degradation was observed for DADA samples. However, identical degradation was observed in all sample types when stress was increased to 1000 s. Intermediate plasma exposure (DSDS process) seems to supress the oxide trap formation as it provides EOT downscaling ability and good reliability performance. The reliability characteristics, when compared with pure HfO2, seem to improve with the addition of ZrO2.

For the purpose of extending the upper temperature limit of metallorganic atomic layer deposition, mixed ligand precursors containing cyclopentadienyl (Cp, C5H5) ligands have been shown to exhibitsuperior thermal stability compared to the widely adopted tetrakis(ethylmethylamino)hafnium (TEMAH) precursor while also possessing adequate vapor pressure characteristics for use in atomic layer deposition (ALD) processing. In order to prevent the deleterious oxidation of the underlying Si from O3 the use of a milder oxidant such as H2O is preferred. Accordingly in this study, we investigated ALD using the liquid precursors CpHf(NMe2)3 and (CpMe)2Hf(OMe)Me in the temperature range 305 – 410 °C with H2O as a co-reactant and compared the film growth and electrical properties with films deposited using a conventional TEMAH/H2O process at 305 °C as well as the same process with an optimized annealing scheme. The CpHf(NMe2)3/H2O process was observed toexhibit a growth-per-cycle (GPC) in the range 0.23 – 0.36 A/cycle ...

We present both EOT scaling and flatband voltage (Vfb) shift for Hf-based high-k containing metal-oxide-semiconductor capacitors (MOSCAPs) due to Al addition into the TiN metal gate. The metal gate was deposited using chemical vapor deposition (CVD) and the Hf-based high-k films were deposited using CVD or atomic layer deposition (ALD) in 300nm deposition chambers. We found that the Vfb shift amount by Al addition into TiN depends on the high-k film (HfO2 vs. HfSiON) as the shift for the HfO2 containing stack was greater than that in the HfSiON containing stack. We also examined the effect of the thermal budget of the MOSCAP flow on the Vfb shift by Al addition into TiN. We observed that the Vfb shift direction by Al addition into TiN was dependant on the MOSCAP flow (gate-first vs. gate-last like) and this Vfb shift behavior can be explained by Al-based dipole and oxygen vacancy models.

not Available.

This work presents a detailed investigation of the deposition of ZrO2 using a metallorganic precursor in a 300 mm wafer processing ALD system. The ZrO2 films in this study were characterized by inline spectroscopic ellipsometry and corona-oxide-semiconductor measurements, and offline Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), Rutherford backscattering spectrometry (RBS), X-ray diffraction (XRD), and transmission electron microscopy (TEM). A growth temperature window between 215 {degree sign}C and 340 {degree sign}C was investigated and the thermal CVD rate was observed to increase above 265 {degree sign}C, thus representing an upper temperature boundary for ALD-dominated growth. For a saturated process at 265 {degree sign}C, a within-wafer non-uniformity of < 2 % for films deposited using 8 cycles or greater was obtained. An in-situ capping with TiN followed by an in-situ post-deposition rapid thermal anneal was also performed in order to assess the thermal stability of the deposited gate stack. For rapid thermal annealed films ({greater than or equal to} 900 {degree sign}C) with a TiN cap, no significant thermally-induced chemical changes were observed while a peak in the XRD spectra attributable to tetragonal and/or cubic phase ZrO2 was observed. Excellent film conformality and coverage over a FinFET structure was observed by TEM.

In this work, we present a study of the growth and electrical characteristics of metalorganic atomic layer deposited (MO-ALD) HfO2 films deposited using a 300 mm Counter-Flow ALD platform. HfO2 films were deposited over a large range of process temperatures, and flow rates in order to fully characterize the MOALD process window. The HfO2 films were characterized using AFM, HRTEM, MEIS, and SIMS. Saturation curves were generated for precursor and ozone oxidant over a 150 ºC process temperature window, using two different flow rates of Hf precursor. The use of water versus ozone as an oxidant was also investigated. Since all depositions take place above the decomposition temperature of the precursor, it is critical to understand and control the rate of thermal decomposition or parasitic CVD in the process in order to realize good uniformity in a traveling wave-type system. Thus, we have measured the rate of thermal CVD over the full range of temperatures. The thermal CVD rate shows a concave Arrhenius behavior as the process rises in temperature and transitions from an ALD dominated growth mechanism to a CVD dominated mechanism. We propose a possible explanation for this behavior. In addition to the growth characteristics, we have investigated the electrical properties of the as-deposited films using in-line Quantox measurements, and gate stack structures using integrated devices. The relationship between process and electrical characteristics will be discussed.

Ultrathin HfO2 films were deposited on various pre-treated Si surfaces by chemical vapor deposition using a hafnium-t-butoxide/O2 process and atomic layer deposition using a tetrakis(ethylmethylamino)hafnium/O3 process. The pre-treatments included aqueous based treatments for chemical oxide growth, HF-last, thermal nitridation, and dry oxidation with and without plasma nitridation. Growth rate differences of CVD grown films were observed, with HF-last based treatments exhibiting the highest barrier to nucleation. ALD grown films exhibited similar growth rates (~1Aå/cycle) and Hf coverage (~29% monolayer coverage/cycle) on all starting surfaces although differences in incubation cycles were observed. Starting surfaces containing nitrogen were shown to have improved nucleation and electron tunneling characteristics with increasing proximity of nitrogen to the starting surface. In device test structures utilizing ALD HfO2, interface nitridation was observed to reduce linear threshold voltage (Vtlin), inversion thickness (Tinv), high field (1 MV/cm) mobility and linear drain current (Idlin), while HF-last treatment was shown to have the highest mobility and Idlin at Tinv = 14.6 Aå.