Search

Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies. This Review examines the development of field-effect transistors based on two-dimensional materials and considers the challenges that need to be addressed for the devices to be incorporated into very large-scale integration (VLSI) technology.

Layered semiconducting transition metal dichalcogenides (TMDs) are promising materials for high-specific-power photovoltaics due to their excellent optoelectronic properties. However, in practice, contacts to TMDs have poor charge carrier selectivity, while imperfect surfaces cause recombination, leading to a low open-circuit voltage (VOC) and therefore limited power conversion efficiency (PCE) in TMD photovoltaics. Here, we simultaneously address these fundamental issues with a simple MoOx (x ≈ 3) surface charge-transfer doping and passivation method, applying it to multilayer tungsten disulfide (WS2) Schottky-junction solar cells with initially near-zero VOC. Doping and passivation turn these into lateral p-n junction photovoltaic cells with a record VOC of 681 mV under AM 1.5G illumination, the highest among all p-n junction TMD solar cells with a practical design. The enhanced VOC also leads to record PCE in ultrathin (2 photovoltaics. This easily scalable doping and passivation scheme is expected to enable further advances in TMD electronics and optoelectronics.

Semiconductors require stable doping for applications in transistors, optoelectronics, and thermoelectrics. However, this has been challenging for two-dimensional (2D) materials, where existing approaches are either incompatible with conventional semiconductor processing or introduce time-dependent, hysteretic behavior. Here we show that low temperature (< 200$^\circ$ C) sub-stoichiometric AlO$_x$ provides a stable n-doping layer for monolayer MoS$_2$, compatible with circuit integration. This approach achieves carrier densities > 2x10$^{13}$ 1/cm$^2$, sheet resistance as low as ~7 kOhm/sq, and good contact resistance ~480 Ohm.um in transistors from monolayer MoS$_2$ grown by chemical vapor deposition. We also reach record current density of nearly 700 uA/um (>110 MA/cm$^2$) in this three-atom-thick semiconductor while preserving transistor on/off current ratio > $10^6$. The maximum current is ultimately limited by self-heating and could exceed 1 mA/um with better device heat sinking. With their 0.1 nA/um off-current, such doped MoS$_2$ devices approach several low-power transistor metrics required by the international technology roadmap, To appear in ACS Nano (2021)

High-density memory arrays require selector devices, which enable selection of a specific memory cell within a memory array by suppressing leakage current through unselected cells. Such selector devices must have highly nonlinear current-voltage characteristics and excellent endurance; thus selectors based on a tunneling mechanism present advantages over those based on the physical motion of atoms or ions. Here, we use two-dimensional (2D) materials to build an ultrathin (three-monolayer-thick) tunneling-based memory selector. Using a sandwich of h-BN, MoS2, and h-BN monolayers leads to an "H-shaped" energy barrier in the middle of the heterojunction, which nonlinearly modulates the tunneling current when the external voltage is varied. We experimentally demonstrate that tuning the MoS2 Fermi level can improve the device nonlinearity from 10 to 25. These results provide a fundamental understanding of the tunneling process through atomically thin 2D heterojunctions and lay the foundation for developing high endurance selectors with 2D heterojunctions, potentially enabling high-density non-volatile memory systems.

Vanadium dioxide (VO2) has been widely studied for its rich physics and potential applications, undergoing a prominent insulator-metal transition (IMT) near room temperature. The transition mechanism remains highly debated, and little is known about the IMT at nanoscale dimensions. To shed light on this problem, here we use ~1 nm wide carbon nanotube (CNT) heaters to trigger the IMT in VO2. Single metallic CNTs switch the adjacent VO2 at less than half the voltage and power required by control devices without a CNT, with switching power as low as ~85 ${\mu}W$ at 300 nm device lengths. We also obtain potential and temperature maps of devices during operation using Kelvin Probe Microscopy (KPM) and Scanning Thermal Microscopy (SThM). Comparing these with three-dimensional electrothermal simulations, we find that the local heating of the VO2 by the CNT play a key role in the IMT. These results demonstrate the ability to trigger IMT in VO2 using nanoscale heaters, and highlight the significance of thermal engineering to improve device behaviour.

We investigate the valley Hall effect (VHE) in monolayer WSe2 field-effect transistors using optical Kerr rotation measurements at 20 K. While studies of the VHE have so far focused on n-doped MoS2, we observe the VHE in WSe2 in both the n- and p-doping regimes. Hole doping enables access to the large spin-splitting of the valence band of this material. The Kerr rotation measurements probe the spatial distribution of the valley carrier imbalance induced by the VHE. Under current flow, we observe distinct spin-valley polarization along the edges of the transistor channel. From analysis of the magnitude of the Kerr rotation, we infer a spin-valley density of 44 spins/μm, integrated over the edge region in the p-doped regime. Assuming a spin diffusion length less than 0.1 μm, this corresponds to a spin-valley polarization of the holes exceeding 1%.

Layered semiconducting transition metal dichalcogenides (TMDs) are promising materials for high-specific-power photovoltaics due to their excellent optoelectronic properties. However, in practice, contacts to TMDs have poor charge carrier selectivity, while imperfect surfaces cause recombination, leading to a low open-circuit voltage (

We discuss the role of aluminum oxide (i.e. Al2O3 when stoichiometric) for transistors and sensors based on oxide semiconductors such as InGaZnO (IGZO) and two-dimensional (2D) semiconductors, such as monolayer MoS2. Aluminum oxide is a well-known capping and dielectric layer in semiconductor technology typically deposited by atomic-layer deposition (ALD), which offers a dense and high-quality film with low gas permeability even when deposited on flexible substrates. However, when deposited at low temperature (< 200°C), aluminum oxide can include a significant amount of fixed charges and defects, which lead to unusual charge trapping and doping effects in semiconductor devices. For example, such charge trapping can cause (apparent) sub-60 mV/decade subthreshold swing at room temperature in IGZO transistors, but can also lead to potential applications in neuromorphic computing. We also discuss effective doping (~1013 cm-2) of 2D semiconductors by thin ALD-grown non-stoichiometric AlOx capping layers. This is achieved with an aluminum seed layer, which enables uniform growth of the subsequently deposited ALD film. This approach leads to a negative shift in threshold voltage, record on-state current (~700 μA/μm) in a monolayer semiconductor, and drastic reduction in contact resistance. Finally, we investigate the passivation effects of Al2O3 capping, which limits the interaction of the underlying semiconductors with ambient air and moisture. We demonstrate improved response in MoS2 temperature sensors and long-term stability in flexible MoS2 transistors (8 months). Further, we evaluate the effects of Al2O3 passivation on IGZO transistors after aging for 80 months.

Layered two-dimensional (2D) materials such as MoS

Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here, we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS

Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS2 grown by chemical vapor deposition. We evaporate thin metal films onto MoS2 and study the interfaces by Raman spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction, transmission electron microscopy, and electrical characterization. We uncover that, 1) ultrathin oxidized Al dopes MoS2 n-type (> 2x10^12 1/cm^2) without degrading its mobility, 2) Ag, Au, and Ni deposition causes varying levels of damage to MoS2 (broadening Raman E' peak from 6 1/cm), and 3) Ti, Sc, and Y react with MoS2. Reactive metals must be avoided in contacts to monolayer MoS2, but control studies reveal the reaction is mostly limited to the top layer of multilayer films. Finally, we find that 4) thin metals do not significantly strain MoS2, as confirmed by X-ray diffraction. These are important findings for metal contacts to MoS2, and broadly applicable to many other 2D semiconductors.

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Two-dimensional (2D) molybdenum trioxide (MoO3) with mono- or few-layer thickness can potentially advance many applications, ranging from optoelectronics, catalysis, sensors, and batteries to electrochromic devices. Such ultrathin MoO3 sheets can also be integrated with other 2D materials (e.g., as dopants) to realize new or improved electronic devices. However, there is lack of a rapid and scalable method to controllably grow mono- or few-layer MoO3. Here, we report the first demonstration of using a rapid (

The ability to actively regulate heat flow at the nanoscale could be a game changer for applications in thermal management and energy harvesting. Such a breakthrough could also enable the control of heat flow using thermal circuits, in a manner analogous to electronic circuits. Here we demonstrate switchable thermal transistors with an order of magnitude thermal on/off ratio, based on reversible electrochemical lithium intercalation in MoS

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO

Demonstration of metamaterials with ultrahigh thermal resistance by phonon-level engineering of heterogeneous 2D monolayers., Heterogeneous integration of nanomaterials has enabled advanced electronics and photonics applications. However, similar progress has been challenging for thermal applications, in part due to shorter wavelengths of heat carriers (phonons) compared to electrons and photons. Here, we demonstrate unusually high thermal isolation across ultrathin heterostructures, achieved by layering atomically thin two-dimensional (2D) materials. We realize artificial stacks of monolayer graphene, MoS2, and WSe2 with thermal resistance greater than 100 times thicker SiO2 and effective thermal conductivity lower than air at room temperature. Using Raman thermometry, we simultaneously identify the thermal resistance between any 2D monolayers in the stack. Ultrahigh thermal isolation is achieved through the mismatch in mass density and phonon density of states between the 2D layers. These thermal metamaterials are an example in the emerging field of phononics and could find applications where ultrathin thermal insulation is desired, in thermal energy harvesting, or for routing heat in ultracompact geometries.

We present novel growth of the two-dimensional (2D) semiconductor MoS 2 directly on oxide/Si sidewalls as deep as $3\ \mu \mathrm{m}$ , demonstrating the first vertical 2D transistors with $I_{\mathrm{o}\mathrm{n}}/I_{\mathrm{off}} > 10^{7}$ and $I_{\mathrm{o}\mathrm{n}}\approx 30\mu \mathrm{A}/\mu \mathrm{m}$ , showing promise for high-density memory selector applications. We also demonstrate direct growth on high-k AbO 3 , an important step towards realizing VLSI-compatible 2D transistors. Our results show that 2D semiconductors can be implemented on non-planar surfaces with amorphous dielectrics for 3D back-end-of-line (BEOL) integration and high-density vertical memory selectors.

As traditional device scaling slows down, three-dimensional (3D) integrated circuits (ICs) are needed to continue Moore’s Law advancements. We show that two-dimensional (2D) semiconductors are promising for heterogeneously integrated 3D ICs owing to their atomically thin nature and unique processing, thermal, and device capabilities.

The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate direct current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO2 film with a metallic carbon nanotube as a nanoscale heater, without using an external capacitor. Compared with VO2-only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to 3 orders of magnitude. This is caused by heating and cooling of the VO2 across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems and a lithography-free technique for energy-scaling of electronic devices that operate via bulk mechanisms.

We investigate the valley Hall effect (VHE) in monolayer WSe

We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current $130\ \mu\mathrm{A}$ and voltage 2 transistor has low off-current due to the large band gap of monolayer MoS 2 $(\mathrm{E}_{\mathrm{g}} > 2\ \text{eV})$ . We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.

Layered two-dimensional (2D) materials such as MoS2 have attracted much attention for nano- and opto-electronics. Recently, intercalation (e.g. of ions, atoms, or molecules) has emerged as an effective technique to modulate material properties of such layered 2D films reversibly. We probe both the electrical and thermal properties of Li-intercalated bilayer MoS2 nanosheets by combining electrical measurements and Raman spectroscopy. We demonstrate reversible modulation of carrier density over more than two orders of magnitude (from 0.8 × 1012 to 1.5 × 1014 cm−2), and we simultaneously obtain the thermal boundary conductance between the bilayer and its supporting SiO2 substrate for an intercalated system for the first time. This thermal coupling can be reversibly modulated by nearly a factor of eight, from 14 ± 4.0 MW m−2 K−1 before intercalation to 1.8 ± 0.9 MW m−2 K−1 when the MoS2 is fully lithiated. These results reveal electrochemical intercalation as a reversible tool to modulate and control both electrical and thermal properties of 2D layers.

The ability to actively regulate heat flow at the nanoscale could be a game changer for applications in thermal management and energy harvesting. Such a breakthrough could also enable the control of heat flow using thermal circuits, in a manner analogous to electronic circuits. Here we demonstrate switchable thermal transistors with an order of magnitude thermal on/off ratio, based on reversible electrochemical lithium intercalation in MoS2 thin films. We use spatially-resolved time-domain thermoreflectance to map the lithium ion distribution during device operation, and atomic force microscopy to show that the lithiated state correlates with increased thickness and surface roughness. First principles calculations reveal that the thermal conductance modulation is due to phonon scattering by lithium rattler modes, c-axis strain, and stacking disorder. This study lays the foundation for electrochemically-driven nanoscale thermal regulators, and establishes thermal metrology as a useful probe of spatio-temporal intercalant dynamics in nanomaterials., Thermal transistors can enable game changing applications in energy harvesting and heat routing. Here, the authors demonstrate reversible thermal modulation of nearly 10 times by ion intercalation in MoS2 nanofilms. A new thermal microscopy technique allows operando imaging of Li ion segregation.

Vanadium dioxide (VO 2 ) is attractive for a variety of applications in optics and electronics, due to its abrupt insulator-metal transition (IMT) with $> 10^{3}\times$ change in resistance near room temperature. Use of VO 2 in devices will require low power switching, with knowledge of the transition mechanism and behaviour down to nanoscale dimensions. To address this challenge, we use metallic carbon nanotubes (CNTs) with diameter ~1 nm [1] to probe nanoscale IMT in VO 2 for the first time. We find that a single CNT locally switches the VO 2 at less than half the voltage and power otherwise required. Furthermore, to understand the nanoscale IMT we use scanning probe microscopy (SPM) techniques to study devices during operation.

Decreasing the subthreshold swing (SS) of field-effect transistors (FETs) to sub-60 mV/decade at room temperature can enable next-generation low-power electronics [1]. Here, we demonstrate steep switching $(SS and high on-current $(I_{\mathrm{ON}}\approx 400\mu \mathrm{A}/\mu \mathrm{m})$ in non-uniformly hole-doped WSe 2 transistors. By setting up large lateral electric field gradients through spatial variation of doping, we deduce that the abrupt switching behavior is consistent with avalanche (impact ionization [2]) of charge carriers, opening up a new approach to achieve low-power transistors based on ultra-thin 2D materials.

We report the fabrication and device characteristics of exfoliated, few-layer, dual-gated ReS2 field effect transistors (FETs). The ReS2 FETs display n-type behavior with a room temperature Ion/I(off) of 10(5). Many devices were studied with a maximum intrinsic mobility of 12 cm(2) · V(-1) · s(-1) at room temperature and 26 cm(2) · V(-1) · s(-1) at 77 K. The Cr/Au-ReS2 contact resistance determined using the transfer length method is gate-bias dependent and ranges from 175 kΩ · μm to 5 kΩ · μm, and shows an exponential dependence on back-gate voltage indicating Schottky barriers at the source and drain contacts. Dual-gated ReS2 FETs demonstrate current saturation, voltage gain, and a subthreshold swing of 148 mV/decade.

The electrical and thermal behavior of nanoscale devices based on two-dimensional (2D) materials is often limited by their contacts and interfaces. Here we report the temperature-dependent thermal boundary conductance (TBC) of monolayer MoS

The electrical and thermal behavior of nanoscale devices based on two-dimensional (2D) materials is often limited by their contacts and interfaces. Here we report the temperature-dependent thermal boundary conductance (TBC) of monolayer MoS$_2$ with AlN and SiO$_2$, using Raman thermometry with laser-induced heating. The temperature-dependent optical absorption of the 2D material is crucial in such experiments, which we characterize here for the first time above room temperature. We obtain TBC ~ 15 MWm$^-$$^2$K$^-$$^1$ near room temperature, increasing as ~ T$^0$$^.$$^6$$^5$ in the range 300 - 600 K. The similar TBC of MoS$_2$ with the two substrates indicates that MoS$_2$ is the "softer" material with weaker phonon irradiance, and the relatively low TBC signifies that such interfaces present a key bottleneck in energy dissipation from 2D devices. Our approach is needed to correctly perform Raman thermometry of 2D materials, and our findings are key for understanding energy coupling at the nanoscale.

Monolayer transition metal dichalcogenide (TMD) materials have exciting potential for applications in spintronics. Due to the monolayer geometry and strong spin-orbit coupling, they are predicted to have a coupled spin and valley Hall effect (SVHE), where valley-polarized conduction carriers have opposite spin [1, 2, 3]. This could provide a valley-preserved spin Hall effect for switching future magnetic memories. WSe2 is an attractive 2D material in this context because of its large valence band spin splitting. Lifetimes of spin and valley polarized carriers in monolayer WSe 2 have been measured from 0.7 ns to 1 μs at 10 K [4, 5, 6]. Such long lifetimes combined with reasonable mobilities lead to spin-valley accumulation that can be imaged via the magneto-optical Kerr effect (MOKE). For use in applications, it is necessary to electrically control the SVHE and push it towards room temperature.

This invited talk will present recent highlights from our research on two-dimensional (2D) materials including graphene, boron nitride (h-BN), and transition metal dichalcogenides (TMDs). The results span from fundamental measurements and simulations, to device- and several unusual system-oriented applications which take advantage of unique 2D material properties. Basic electrical, thermal, and thermoelectric properties of 2D materials will also be discussed.

Doping of two-dimensional (2D) semiconductors often utilizes charge transfer techniques that are not compatible with standard CMOS fabrication and are unstable over time. Sub-stoichiometric oxides have demonstrated stable 2D material doping [1], but often degrade the subthreshold swing (S) and current on/off ratio (I max /I min ) of a device. Here, we demonstrate that AlOx can n-dope monolayer (1L) MoS2 while preserving Imax/Imin and S. The AlO x doping significantly reduces the contact resistance (to 480 Ω·μm) while preserving the mobility (∼34 cm2V−1s−1) and S, ultimately achieving record on-current of 700 μA/μm for a monolayer semiconductor. We also present a model for the effect of interface traps on the transfer characteristics, which explains the experimentally obtained results.

This invited talk will present recent highlights from our research on two-dimensional (2D) materials including graphene, boron nitride (h-BN), and transition metal dichalcogenides (TMDs). The results span from fundamental measurements and simulations, to device- and several unusual system-oriented applications which take advantage of unique 2D material properties. Basic electrical, thermal, and thermoelectric properties of 2D materials will also be discussed.

The advancement of nanoscale electronics has been limited by energy dissipation challenges for over a decade. Such limitations could be particularly severe for two-dimensional (2D) semiconductors integrated with flexible substrates or multilayered processors, both being critical thermal bottlenecks. To shed light into fundamental aspects of this problem, here we report the first direct measurement of spatially resolved temperature in functioning 2D monolayer MoS

We fabricate and characterize a set of dual-gated graphene field effect transistors using a novel physical vapor deposition technique in which titanium is evaporated onto the graphene channel in 10 Å cycles and oxidized in ambient to form a top-gate dielectric. A combination of X-ray photoemission spectroscopy, ellipsometry, and transmission electron microscopy suggests that the titanium is oxidizing in situ to titanium dioxide. Electrical characterization of our devices yields a dielectric constant of κ = 6.9 with final mobilities above 5500 cm(2)/(V s). Low temperature analysis of the gate-leakage current in the devices gives a potential barrier of 0.78 eV in the conduction band and a trap depth of 45 meV below the conduction band.

In summary, we demonstrated WSe2 FETs contacted with thin metallic WTe2, at channel lengths down to 90 nm and current saturation up to 60 μA/μm. A temperature-dependent study suggests the presence of an intrinsic vdWg at the 2D-2D contact. Thus, ultra-thin WTe2 could be preferred to graphene as a contact depinning layer. This work was supported in part by the AFOSR, NSF-EFRI, and Stanford SystemX.

We studied power dissipation in 1L MoS2 devices using Raman thermometry for the first time. We uncovered non-uniformities of power dissipation and the important role of the MoS2-substrate interface thermal resistance. These results provide critical insights for thermal design of devices based on 2D materials. This work was supported by the AFOSR, NSF EFRI 2-DARE, and Stanford SystemX.

Transistors based on two-dimensional (2D) materials often exhibit hysteresis in their electrical measurements, i.e. a dependence of measured current on voltage sweep direction due to charge trapping. Here we demonstrate a simple pulsed measurement technique which reduces this hysteretic behavior, enabling more accurate characterization of 2D transistors. We compare hysteresis and charge trapping in four types of devices fabricated from both exfoliated and synthetic MoS2, with SiO2 and HfO2 insulators, using DC and pulsed voltage measurements at different temperatures. Applying modest voltage pulses (~1 ms) on the gate significantly reduces charge trapping and results in the elimination of over 80% of hysteresis for all devices. At shorter pulse widths (~1 µs), up to 99% of hysteresis is reduced for some devices. Our measurements enable the extraction of a unique value of field-effect mobility, regardless of voltage sweep direction, unlike measurements that rely on forward or backward DC measurements. This simple and reproducible technique is useful for studying the intrinsic properties of 2D transistors, and can be similarly applied to other nanoscale and emerging devices where charge trapping is of concern.

We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.