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This paper presents a low-power implementation of the A8051 processor. It employs an adaptive pipeline structure that allows to skip a redundant stage operation and to combine with the neighboring empty stage. The processor has three features to reduce the power dissipation as well as to improve performance: multilooping control for multicycle instructions, branch predictor for unconditional branches, and a single threading in the EXE stage. The experimental results show that A8051 runs about 1.8 times faster than the synchronous counterpart, CIP51 [reported in the HC8051F0xx Family Datasheet (2002)]. In terms of [Et.sup.2], our implementation shows 15 times higher efficiency than that of asynchronous counterpart developed by the Nanyang University [Chang and Gwee (2006)]. Index Terms--Asynchronous logic circuits, computer architecture, microprocessor, pipelines, power analysis.

Abstract: The great advancement in computer architecture and cache memory design and technology had a considerable influence on the way computer architecture was taught in universities. This requires students to [...]

3-D video will be the most prominent video technology in the next generation. Among the 3-D video technologies, stereo video systems are considered to be realized first in the near future. Stereo video systems require double bandwidth and more than twice the computational complexity relative to mono-video systems. Thus, an efficient coding scheme is necessary for transmitting stereo video. In this paper, a new structure of prediction core in stereo video coding systems is proposed from the algorithm level to the hardware architecture level. The joint prediction algorithm (JPA), which combines three prediction schemes, is proposed for high coding efficiency and low computational complexity. It makes the system outperform MPEG-4 temporal scalability and simple profile by 2-3 dB in rate--distortion performance. Besides, JPA also utilizes the characteristics of stereo video and successfully reduces about 80% computational complexity. Then, a new hardware architecture of the prediction core based on JPA and a modified hierarchical search block-matching algorithm is proposed. With a special data flow, no bubble cycles exist during the block-matching process. The proposed architecture also adopts the near-overlapped candidates reuse scheme to save the heavy burden of data access. Besides, both on-chip memory requirement and off-chip memory bandwidth can be reduced by the proposed new scheduling. Compared with the hardware requirement for the implementation of full search block-matching algorithm, only 11.5% on-chip SRAM and 3.3% processing elements are needed with a tiny PSNR drop, making it area-efficient while maintaining high stereo video quality and processing capability. Index Terms--Hardware architecture, joint prediction algorithm (JPA), stereo video coding, 3-D video.

Abstract: To design a hardware system we may use generated Intellectual Property (IP) cores from a library with optimized parameters. The IP parameters are area minimization, memory use optimization and [...]

The limited bandwidth and the increase in power dissipation at longer communication distances and higher bit rates will create a major communication bottleneck in high-performance computing systems (HPCS), affecting not only their performance, but also their scalability. As a solution, we propose an optical-interconnect-based architecture for HPCS called reconfigurable all-photonic interconnect for parallel and distributed systems (RAPID) that alleviates the bandwidth density, optimizes power consumption, and enhances scalability. We also present two cost-effective design alternatives of the architecture, a modified version called M-RAPID and an extended version called E-RAPID that minimizes the cost of the interconnect based on the number of transmitters required. We perform a detailed simulation of the proposed RAPID architecture and compare it to several electrical HPCS interconnects. Based on the performance study, RAPID architecture shows 30%-50% increased throughput and 50%-75% reduced network latency as compared to HPCS electrical networks. OCIS codes: 200.0200, 200.4650.

Abstract: This study proposes new Home Agent architecture and algorithms for real-time mobility management in mobile IP networks. The proposed architecture and algorithms offer a better performance based on the [...]

Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and massively parallel architectures, demand faster, more efficient, and more scalable cache coherence schemes. In devising more cost-efficient schemes, formal insights into a system model is deemed useful. We. in this paper, build formalisms for execution in cache based Distributed shared-memory multiprocessors (DSM) obeying Release Consistency model, and derive conditions for cache coherence. A cost-efficient cache coherence scheme without directories is designed. Our approach relies on processor directed coherence actions, which are early in nature. The scheme exploits sharing information provided by a programmer-centric framework. Per-processor coherence buffers (CB) are employed to impose coherence on live shared variables between consecutive release points in the execution. Simulation of 8 entry, 4-way associative CB based system achieves a speedup of 1.07-4.31 over full-map 3-hop directory scheme for six of the SPLASH-2 benchmarks. KEY WORDS: Distributed shared-memory multiprocessor; cache coherence; programmer-centric framework; release consistency memory model; performance evaluation.

The multiview storage system (MVSS), a storage system for active devices, is described and discussed.

Use of User-Level Memory Thread (ULMT) for correlation prefetching is proposed and discussed.

An analytical model for evaluation of the performance of shared-memory architectures with instruction-level parallelism (ILP) processors is presented and discussed.

This article presents a new and highly accurate method for branch prediction. The key idea is to use one of the simplest possible neural methods, the perceptron, as an alternative to the commonly used two-bit counters. The source of our predictor's accuracy is its ability to use long history lengths, because the hardware resources for our method scale linearly, rather than exponentially, with the history length. We describe two versions of perceptron predictors, and we evaluate these predictors with respect to five well-known predictors. We show that for a 4 KB hardware budget, a simple version of our method that uses a global history achieves a misprediction rate of 4.6% on the SPEC 2000 integer benchmarks, an improvement of 26% over gshare. We also introduce a global/local version of our predictor that is 14% more accurate than the McFarling-style hybrid predictor of the Alpha 21264. We show that for hardware budgets of up to 256 KB, this global/local perceptron predictor is more accurate than Evers' multicomponent predictor, so we conclude that ours is the most accurate dynamic predictor currently available. To explore the feasibility of our ideas, we provide a circuit-level design of the perceptron predictor and describe techniques that allow our complex predictor to operate quickly. Finally, we show how the relatively complex perceptron predictor can be used in modern CPUs by having it override a simpler, quicker Smith predictor, providing IPC improvements of 15.8% over gshare and 5.7% over the McFarling hybrid predictor. Categories and Subject Descriptors: C.1.1 [Computer Systems Organization]: Processor Architectures--Single data stream architectures General Terms: Performance Additional Key Words and Phrases: Branch prediction, neural networks

The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video. Index Terms--Computer architecture, digital signal processors, very-large-scale integration, video signal processing.

We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods. Index Terms--All-binary motion estimation (ABME), binary motion estimation, fast motion estimation, fast motion search, multiresolution.

The robust stability of uncertain linear continuous-time systems with time delay in the state and subject to saturating controls is addressed. The uncertainties are of the polytopic type. The method of synthesis via linear matrix inequalities consists in determining simultaneously a state feedback control law and the associated domain of safe admissible states for which the robust stability of the closed-loop system is guaranteed, when control saturations effectively occur. Keywords: Delay systems; Robust stability; Polytopic uncertainties; Saturating controls; Linear matrix inequalities; Delay-independent stability

Computer rendering is used to simulate the appearance of lighted objects for applications in architectural design, for animation and simulation in the entertainment industry, and for display and design in […]