Search

We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries. digital memory | hybrid circuits | three-dimensional integrated circuits www.pnas.org./cgi/doi/10.1073/pnas.0906949106

The optimization of the noise performance of integrated complementary metal-oxide semiconductor (CMOS) charge amplifiers is studied in detail considering accurate 1/f noise modeling for the input metal-oxide semiconductor field-effect transistor (MOSFET) biased in a strong inversion-saturation region. This paper aims to generalize and correct previously published analyses which have been based on two limiting and sometimes not applicable assumptions: a fixed MOSFETs bias current and the general validity of the McWhorter 1/f noise model. This study considers the two main 1/f noise models: 1) the mobility fluctuation, known as [DELSTA][micro] or Hooge model, which is followed by p-channel MOSFETs and 2) the carriers number fluctuation, also known as AN or McWhorter model, which is applicable only for n-channel MOSFETs. The front-end noise optimization is made with the 1/f component alone, thus determining the ultimate performance, and also considering the presence of series and parallel white noise sources. It is shown that different design criteria are valid of p- or n-channel MOSFETs: the [DELTA][micro] model results in an optimum bias current and a different optimum gate width with respect to [DELTA]N model. Two-dimensions suboptimum noise minimization criteria are derived when power or area constraints are imposed to the circuit design. Starting from experimental data on CMOS 1/f noise, examples of application of the presented analysis are shown to predict the lower limits of the 1/f noise contribution for the currently available CMOS technologies. Index Terms--Charge amplifier, complementary metal-oxide semiconductor (CMOS) integrated circuit (IC), integrated circuits (ICs), low-noise circuit, 1/f noise.

This work is aimed at defining the architecture of a new digital ASIC, namely Slow Control Logic (SCL), which will be designed and fabricated in a commercial 130 nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics proposed for future high-energy physics experiments at the super-Large Hadron Collider (SLHC), CERN, Geneva. The GBT link provides a transparent transport layer between the SCL and control electronics in the counting room. It will be provided with rad-hard redundant logic for critical circuits. The project follows a set of designs that were recently developed via a 250 nm CMOS technology for LHC experiments. Since this 250 nm specific technology used to design ASICs for the LHC will no longer be available as it was in the past, requesting an update technology for future experiments must be satisfied in any case. A test chip that implements three different redundant methodologies against Single Event Effects is also described. Index Terms--GBT, radiation hardness, SCL, single event effects.

We report the observation of performance degradation in a detector consisting of a phosphor screen and a CMOS (complementary metal-oxide-semiconductor) photodiode array under the continuous irradiation of 45-kVp x-rays. The performance was assessed in terms of dark pixel signal, dynamic range, modulation-transfer function (MTF), noise-power spectrum (NPS), and detective quantum efficiency (DQE). From the measurement results, it has been observed that the increase of dark pixel signal and the related noise gradually reduces the dynamic range as the cumulative input exposure to the detector increases. Severe degradation in NPS was observed, which gives rise to reduction in DQE as the cumulative input exposure increases. With carefully updated offset and gain correction, however, we can overcome the detrimental effects of increased dark current on NPS and DQE. Index Terms--CMOS detector, CMOS devices, detective quantum efficiency, digital radiography, fiat-field correction, image evaluation, image sensors, noise-power spectrum, radiation effects, X-ray imaging.

Monolithic CMOS cameras for direct imaging in electron microscopy and other radiation imaging applications have been developed and have been used to capture images with high signal to noise and resolution. Based on CMOS Active Pixel Sensor (APS) technology, the arrays use an 8 to 20 [micro]m epitaxial layer that acts as a thicker sensitive region for the liberation and collection of ionization electrons resulting from impinging charged particles. This results in a 100% fill factor and a far larger signal per incident charged particle than a typical CMOS photodiode could provide. The per-pixel CDS scheme discussed in this paper has demonstrated reductions in kT/C noise by a factor of four, to 11 electrons RMS at room temperature. The CDS scheme requires only one read instead of the two reads plus pre- and post-integration subtraction required by traditional CDS, and is hence faster than alternate schemes. In addition, the test device was used in the observation of Random Telegraph Signal noise (RTS) in small-capacitance pixels under different [V.sub.gs] conditions. Index Terms--Image sensors, particle tracker, radiation detectors, smart pixels.

SSPMs fabricated using CMOS technology consisting of arrays of 30- and 50- [micro]m square pixels in 1.5 mm x 1.5 mm total area with high, 61%, and low, 29%, fill factors (packing density) were used to measure the photon intensity resolution for a pulsed laser light source. Different sources of noise (i.e., cross talk, dark counts, and electronic) have a deleterious effect on the energy resolution, and this work looks at the relative sizes of these contributions. Even though noise effects increase with larger fill factors and active area, this work examines the trade-off between these noise terms and the improvement in the detection efficiency with increased excess bias or fill factor. The energy resolutions from various gamma rays, including 122 keV, 511 keV, 662 keV, and 1275 keV, measured with an LYSO scintillation crystal (1.5 mm x 1.5 mm x 3 mm) were compared to the pulsed laser results to examine all noise contributions to the energy resolution. The SSPM response can be described by a binomial function. When greater than 70% of the pixels are triggered, the energy resolution contains a substantial contribution from the detector response that arises from a binomial detector response of the SSPM, which contains a finite number of pixel elements. Index Terms--Complementary metal-oxide semiconductor (CMOS), LYSO, SiPM, solid-state photomultipler, solid-state photomultiplier (SSPM).

This brief describes low-cost on-chip measurement circuits for jitter transfer and supply sensitivity of phase-locked loops (PLLs) and delay-locked loops (DLLs). Unlike previous works that measured the frequency-domain responses, the proposed circuits measure the time-domain responses of the PLL/DLL to the periodic disturbances applied to either its input clock phase or its supply voltage. A synchronous sampling technique accurately measures the PLL/DLL's periodic response while suppressing the unrelated noises and interferences via averaging. The synchronous sampler outputs either dc voltage or digital values, making it suitable for low-cost characterization and production tests. The procedure for estimating the frequency-domain transfer functions from the measured time-domain responses is outlined. The jitter transfer and supply sensitivity measurements were demonstrated with a PLL fabricated in 0.13-[micro]m CMOS. Compared with the PLL that occupied 1.1 x 0.46 [mm.sup.2] and dissipated 36 mW from a 1.2-V supply, the on-chip measurement circuits occupied only 0.014 [mm.sup.2] and dissipated only 2.6 mW. Index Terms--CMOS, jitter transfer function, on-chip measurement, phase-locked loop (PLL), supply sensitivity.

This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a [V.sub.GS] lower than zero [K39.sub.m] point. This [V.sub.GS] difference is attributed to the nonlinear output conductance and the cross terms using a Volterra-series-based IP3 expression. The impact of these nonlinearities is quantified using simulated I-V and device small-signal parameters extracted from S-parameter simulation. The scaling factors of the nonlinearities causes a decrease of IP3 sweet spot [J.sub.DS] as device size increases. The IP3 expression can accurately predicts the device size dependence of IP3 sweet spot. The frequency dependence of IP3 is determined by the small signal capacitance. Thus, the frequency dependence is very weak and negligible for a small device. For a large device, not only gate-source capacitance and drain-bulk capacitance, but also gate--drain capacitance are important. To determine the value of IP3 accurately, a more complete equivalent circuit of the MOS transistor must be used in Volterra-series analysis. The VDS dependence of the IP3 sweet spot [V.sub.GS] is primarily due to drain induced barrier lowering. Index Terms--BSIM4, drain induced barrier lowering (DIBL), linearity, low-noise amplifier (LNA), RF CMOS, threshold voltage, Volterra series.

In this paper, the effects of forward body bias (FBB) on high-frequency noise performance in deep-submicrometer CMOS transistors are presented. It was observed that noise parameters [NF.sub.min] and [R.sub.n] in both N and PMOS increased significantly under FBB. FBB may appear as a great concern in the low noise circuit design. This is in contrast with the improvement of other device parameters induced by FBB, such as reduction of threshold voltage ([V.sub.TH]), and increase in speed. The underlying physical mechanisms for the noise increase in N and PMOS were found to be different. In NMOS, high-frequency noise behavior can be well explained by a combinational effect between substrate resistance noise and nonequilibrium channel noise. However, increase of noise in PMOS was found to be mainly due to the substrate resistance noise. The contribution of nonequilibrium channel noise is trivial. Index Terms--Body bias, channel noise, high-frequency noise, MOSFETs, noise modeling, nonequilibrinm channel noise, RF noise, semiconductor device noise, substrate resistance noise.

Single event latchup (SEL) in a 65 nm CMOS SRAM technology due to heavy ions is observed and device sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. Experimental results show the importance of testing at multiple lateral beam orientations to properly characterize device sensitivity. Index Terms--65 nm, azimuthal angle, grazing angle, lateral angle, radiation effects, single event latchup.

We compare four circuit methods for Single Event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and Triple Modular Redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture. Index Terms--Complementary metal-oxide-semiconductor (CMOS), digital circuits, field programmable gate array (FPGA), radiation-hardening, sequential circuits, single event.

This paper presents a charge pump-phase locked loop (CP-PLL) that utilizes a frequency-modulated analog-to-digital converter (FM-ADC) as part of a calibration circuit to compensate for process variations and intemperate operating environments. The calibration circuitry first detects the shift in operating conditions, and then dynamically adjusts the loop bandwidth back to its nominal range to guarantee phase lock for all four process corners and the typical case, and across the telecommunications temperature range of 0 to 80[degrees]C. Calibration comes at the expense of a worst case increase in lock time of 15% and increase of close-in phase noise of 13% for the PLL architecture examined. This self-calibrating PLL, including the FM-ADC, are designed and laid out in TSMC's 0.18-[micro]m RF CMOS process (TSMC18RF). Index Terms--Analog-to-digital converters (ADCs), phase-locked loops (PLLs), self-calibration.

This paper describes the implementation of a smart-optical detector array for detection and concentration measurement of biochemical parameters in physiological fluids. Its application is in the low-cost microchip size analytical laboratories that use colorimetric detection, by optical absorption, as the analytical technique. The microlaboratory structure is composed of a microplate cuvette array containing the physiological fluids into analysis and an optical detector array underneath, which quantifies the light absorbed by those fluids. The detectors, together with their analog-to-digital (A/D) conversion, are designed and fabricated using a standard CMOS process. The on-chip A/D conversion is performed, simultaneously, using a 1-b first-order sigma-delta converter for each optical detector. The output signal of the device is a bit stream containing information about the absorbed light, which allows simple microcontroller interfacing. The proposed architecture has the main advantage of performing the simultaneous measurement of the light absorbed by the fluids, which avoids the errors that can be introduced due to light fluctuations in uncontrolled environments. In addition, the architecture allows on-chip calibration during each measurement. This means that the device can be reliably used in environments with noncalibrated light sources, e.g., in a doctor's office. The A/D conversion design described here represents significant improvements when compared with the existing designs. Moreover, the microlaboratory application holds great promise, by both improving benefits (quality of health services provided) and reducing costs (of physiological fluid analysis services). Index Terms--Biochemical parameters, optical absorption, sigma-delta converter, smart-optical detector array.

This paper describes a multiband CMOS chip-set for indirect and direct conversion base station receivers. The chip set consists of a low-noise amplifier (LNA), and a down-converter which includes a passive resistive mixer and a local-oscillator balun. The 0.25-[micro]m CMOS receiver chip set, biased at 3 V, meets normal DCS1800, PCS1900, and Universal Mobile Telecommunication System (UMTS) base station specifications in heterodyne and homodyne architectures. In a heterodyne architecture, an third-order input intercept point (IIP3) higher than -5 dBm was achieved with a noise figure (NF) lower than 4.5 dB for the complete receiver chain in the DCS1800, PCS1900, and UMTS bands. In a homodyne architecture, IIP3 and second-order input intercept point (IIP2) values better than 0 and 40 dBm, respectively, were achieved for the complete receiver chain in all three bands, with an NF of less than 6 dB. A dedicated DCS1800 heterodyne receiver based on this chip-set was developed, meeting and exceeding the specifications, with a NF of 5.8 dB and IIP3 of 0.4 dBm. This is believed to be the first CMOS receiver chip set that meets second and third-generation base station specifications in indirect and direct conversion architectures. Index Terms--Base station, CMOS integrated circuits, DCS 1800, direct conversion, heterodyne, PCS1900, receiver, Universal Mobile Telecommunication System (UMTS).

The use of the multipartite table methods (MTMs) to implement high-performance direct digital frequency synthesizers (DDFSs) is investigated in this paper. A closed-form expressions for the spurious-free dynamic range (SFDR) is obtained when a single table of offset (TO) is used in the multipartite approximation. In this case, the optimal design that minimizes storage requirement for a given SFDR can be obtained analytically. A numerical algorithm is also presented to obtain the optimal design also when two or more TOs are employed is the approximation. The VLSI implementation results and the comparison with previously proposed DDFS architectures demonstrate the effectiveness of mnitipartite table methods for the realization of high performance direct digital synthesizers. Index Terms--CMOS digital integrated circuits, direct digital synthesis (DDS), direct digital frequency synthesizers (DDFS), frequency synthesis, multipartite table method (MTM), phase-to-sinusoid amplitude conversion, read-only memory (ROM) compression.

This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18-[micro]m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss. Index Terms--Bandpass filters, CMOS technology, millimeterwave, thin-film microstrip (TFMS) structure.

This paper introduces active transformer currentmode phase-locked loops (PLLs). The proposed PLLs replaces the RC loop filter of voltage-mode PLLs with an active transformer loop filter to take the advantage of their large inductance and small silicon area. A current-controlled LC oscillator with active inductors is employed to further reduce silicon area. The sensitivity of the cutoff frequency of active transformer loop filter to supply voltage fluctuation and process variation is analyzed. A 3-GHz PLL has been implemented in TSMC 0.18-[micro]m 6-metal 1.8-V CMOS technology and analyzed using SpectreRF with BSIM3v3 device models and Verilog-AMS from Cadence Design Systems. The lock time of the PLL is 60 ns. The power consumption and phase noise of the PLL are 16 mW and--100 dBc/Hz at 1-MHz frequency offset, respectively. The layout area of the PLL is 2800 [micro][m.sup.2]. Index Terms--CMOS active inductors and transmitters, current-mode circuits, phase-locked loops (PLLs).

A new digitally programmable universal current-mode biquad filter is proposed. The filter is based on digitally controlled current followers (DCCFs). It utilizes gains of the DCCFs to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. All parameters of the proposed filter can be adjusted independently. Experimental results obtained from a 0.35-[micro]m standard CMOS chip are provided. Index Terms--CMOS analog integrated circuits, current-mode (CM) filters.

In this paper, design techniques for an integrated RF bandpass filter are discussed. A novel wide-tuning high-Q active bandpass filter utilizing the active inductors is presented. Issues of the active inductor related to Q-enhancement, noise, linearity, and stability are considered. The circuit has been fabricated in an 0.18-[micro]m CMOS process, and the filter occupies the active area of 150 x 200 [micro][m.sup.2]. Measurement results show that the filter centered at 3.82 GHz with about 36-MHz bandwidth (3-dB) is tunable in frequency from about 1.92 to 3.82 GHz, and it exhibits--15-to 1-dB compression point at 2.44 GHz with approximately 60-MHz bandwidth while the dc power consumes 10.8 mW. Index Terms--Active bandpass filters, active inductors, multiband RF front-ends, Q-enhancement, stability.

The design of a fully integrated CMOS low noise amplifiers (LNA) for ultra-wide-band (UWB) integrated receivers is presented. An original LC input matching cell architecture enables fractional bandwidths of about 25%, with practical values, that match the new ECC 6-8.5-GHz UWB frequency band. An associated design method which allows low noise figure and high voltage gain is also presented. Measurements results on an LNA prototype fabricated in a 0.13-[micro]m standard CMOS process show average voltage gain and noise figure of 29.5 and 4.5 dB, respectively. Index Terms--Low-noise amplifiers (LNAs), ultra wide band (UWB), CMOS integrated circuits.

and V-band CMOS differential subharmonic injection-locked frequency triplers (ILFTs) are proposed, analyzed, and designed. Based on the proposed ILFT structure, models for the injection-locking range and the output phase noise are developed. A K-band ILFT is designed and fabricated using 0.18- [micro]m standard CMOS technology. The measured injection-locking range is 1092 MHz with a dc power consumption of 0.45 mW and an input injection power of 4 dBm. The harmonic rejection ratios are 22.65, 30.58, 29.29, 40.35 dBc for the first, second, fourth, and fifth harmonics, respectively. The total injection-locking range of the K-band ILFT can achieve 3915 MHz when the varactors are used and the dc power consumption is increased to 2.95 mW. A V-band ILFT is also designed and fabricated using 0.13-[micro]m standard CMOS technology. The measured injection-locking range is 1422 MHz with 1.86-mW dc power consumption and 6-dBm input injection power. The injection-locking range of the proposed ILFT is similar to the tuning range of a conventional varactor-tuned bulk-CMOS voltage-controlled oscillator (VCO). Moreover, the proposed ILFT has a greater output power and a lower dc power consumption level than a VCO. As a result, it is feasible to use the proposed ILFT in low-power millimeter-wave synthesizers. Index Terms--Frequency tripler, injection-locked oscillators (ILOs), RF CMOS, voltage-controlled oscillator (VCO).

A novel modified resistive feedback structure for designing wideband low-noise amplifiers (LNAs) is proposed and demonstrated in this paper. Techniques including feedback through a source follower, an R-C feedback network, a gate peaking inductor inside the feedback loop, and neutralization capacitors are used. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Two LNAs, LNAI and LNA2, were fabricated using a TSMC digital 90-nm CMOS technology. Both chips were tested on board using chip-on-board packages with ESD diodes added at the inputs and outputs. LNA1 achieves a 3-dB bandwidth of 9 GHz with 10 dB of power gain and a minimum noise figure (NF) of 4.2 dB. LNA2 achieves a 3-dB bandwidth of 3.2 GHz with 15.5 dB of power gain and a minimum NF of 1.76 dB. The two LNAs have third-order intermodulation intercept points of -8 and -9 dBm. Their power consumptions are 20 and 25 mW with a 1.2-V supply, respectively. Index Terms--CMOS, electrostatic devices (ESDs), low-noise amplifier (LNA), multiband receiver, resistive feedback, ultra-wideband (UWB).

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-[micro]m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288 x 291 [micro]m or 0.08 [mm.sup.2] of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than -12 and -25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8-10 GHz, while the power consumption is approximately 22 mW. Index Terms--CMOS RF integrated circuit (RFIC), distributed amplifiers, low-noise amplifiers (LNAs), multilayer inductors, ultra-wideband (UWB) circuits, UWB systems.

A new configuration is proposed for an active balun, which uses a cascode and cascade pair with the shared input transistor. It is designed in the IBM 8HP 130-nm BiCMOS process, which operates over a broad bandwidth up to 17 GHz where the imbalance of the differential output is less than 1.8 dB in amplitude and less then 10[degrees] in phase, over the input's dynamic range of -25-5 dBm, under the dc power consumption of 198.8 mW. The circuit contains no internal dc blocking capacitors so that the bandwidth's lower end frequency best extends as close to dc as possible. The circuit contains only one line inductor with the value of 0.2 nil, and the compacted layout is expected to fit in limited chip areas as small as 0.2 mm x 0.2 mm, which makes them well suited for built-in self-test applications, as well as general differential circuits requiring compact-sized broadband baluns. Index Terms--Active balun, broadband balun, built-in self-test (BiST), combined cascode-cascade balun (C3 balun), CMOS balun.

In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a [G.sub.m]-boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-[micro]m CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured [P.sub.in-1 dB] and [IIP.sub.3] are -18 and -8.6 dBm, respectively. For the LNA with a [G.sub.m]-boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW. Index Terms--Body transconductance, folded cascode, forward body bias, [G.sub.m] boosting, low-noise amplifiers (LNAs), low power, low voltage.

A novel CMOS transmit/receive (T/R) switch suitable for ultra-low-voltage operations is presented in this paper. Due to the use of LC resonators in the receiving and transmitting paths, enhanced performance in terms of insertion losses and isolation can be achieved. In addition, the forward-body-bias and body-floating techniques are also introduced to minimize the on-resistance of the MOSFETs at a reduced bias voltage. Using a standard 0.18-[micro]m CMOS process, a 5.2-GHz asymmetric T/R switch based on the proposed architecture is implemented. With a supply voltage of 0.6 V, the fabricated circuit exhibits 1.56-dB insertion loss, 17-dB isolation, and ll.2-dBm [P.sub.in-1] dB in the receiving mode while the measured results in the transmitting mode are 2.02 dB, 31 dB, and 29.6 dBm, respectively. Index Terms--Body floating, forward body bias, LC resonators, single pole double throw, transmit/receive (T/R) switches, ultra-low voltage.

This paper presents a novel design of monolithic 2.5-GHz 4 x 4 Buffer matrix in 0.18- Sheng- [micro]m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Buffer matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of 454 [+ or -] 3[degrees], 135 d= 4[degrees], -45 [+ or -] 3[degrees], and -135 [+ or -] 4[degrees] with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1 x 4 monopole antenna array. The generated beams are pointing to -45[degrees], -15[degrees], 15[degrees], and 45[degrees], respectively, with less than 1[degrees] error, which agree very well with the predictions. This Buffer matrix consumes no dc power and only occupies the chip area of 1.36 x 1.47 [mm.sup.2]. To our knowledge, this is the first demonstration of the single-chip Buffer matrix in CMOS technology. Index Terms--Antenna array, beamforming, Buffer matrix, quadrature coupler, reflection-type phase shifter (RTPS), transformer.

A load-shared CMOS power amplifier (PA) for 1.8-GHz polar transmitter applications has been implemented in standard 0.18-[micro]m CMOS technology and fully characterized to demonstrate its efficiency boosting technique in low power mode. With the aid of cascode amplifiers, the load-shared configuration achieves efficiency improvement at low supply voltage in a polar transmitter. A differential class-E amplifier with a parallel resonant circuit is analyzed and incorporated in the load-shared PA. The load-shared configuration is composed of driver amplifiers (DAs) and PAs whose output loads are shared. The DA has a constant gate voltage biasing of a cascode amplifier for efficiency boosting, whereas the PA has a self-biased cascode configuration to be turned on and off by a supply voltage. The measurement results of the load-shared configuration show a drain efficiency increase from 6% to 30% at 16-dBm output power compared with a conventional self-biased cascode amplifier. The load-shared PA is reported with 35.6% of power-added efficiency and 32.2 dBm of output power at 1.88 GHz. Index Terms--Cascode amplifiers, CMOSFET power amplifiers (PAs), mode locking, monolithic microwave integrated circuit (MMIC) PAs, polar transmitters.

A new phase-domain all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. In this brief, we propose time-domain modeling and simulation techniques of the ADPLL that are well suited for system analysis using high-level programming languages, e.g., Matlab. They are based on the event-driven principles inherent in hardware description languages, e.g., VHDL, and enable the development of accurate and time-efficient behavioral models. The proposed techniques are demonstrated and validated through experimental results for a GSM standard. Index Terms--All-digital phase-locked loop (ADPLL), CMOS, digitally controlled-oscillator (DCO), event driven, GSM, mobile phones, phase detection, phase noise, simulation, time-domain modeling, time-to-digital-converter (TDC), wireless.

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-[micro]m CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-[V.sub.PP] input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption. Index Terms--Analog CMOS circuits, flipped voltage follower (FVF), linear circuits, low-power and low-voltage CMOS circuits, operational transconductance amplifier (OTA), quasi-floating-gate transistors.

We present a mathematical analysis of the common-mode instability and power back-off feature of a transformer-coupled Class-AB differential power amplifier (PA). The efficient impedance matching of the transformer combiner and efficiency improvement at power back-off, a major benefit of this structure, are illustrated. In addition, an analytical model is derived to predict the common-mode oscillations in PA. The analytical results, based on a simple hand-calculation model for the transistor, show good agreement with simulation results using complete 90-nm models. Two methods to suppress the common-mode oscillations are investigated and analyzed in detail. Index Terms--CMOS, power amplifiers (PAs), power combining, stability.

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate > 70 % of SETs longer than 1 ns. Index Terms--CMOS, guard band, parasitic bipolar, pulse width, single event transient (SET), single event upset (SEU), soft error, well contact.

We evaluated X-ray image performance for several scintillators and a CMOS APS imager by both diagnostic radiography and mammography conditions. Commercially available scintillators such as Lanex screen, needle structured CsI (T1), and fiber optic structured CsI (T1) were coupled with a CMOS APS imager. The X-ray machines used in this study were fixed tube voltage of 80 kVp and variable tube current over 0.33 mA using LISTEM[TM] for diagnostic radiography, and fixed tube voltage of 28 kVp and variable tube current over 16 mA using Alpha-ST[TM] for mammography. We used the RadEye1[TM] CMOS APS imager having an active area of 25 mm by 50 mm with the pixel size of 48 [micro]m. Index Terms--CMOS active pixel sensor, diagnostic radiography, mammography, scintillators.

An ultra-compact monolithic microwave integrated circuit active variable phase shifter is proposed and implemented using CMOS technology. It is a reflective-type phase shifter consisting of a compact three-transistor active circulator and a second-order LC network. The use of an active inductor in the second-order LC network makes this phase shifter all active and ultra compact with a size of only 0.357 [mm.sup.2] including bonding pads. The phase shifter was designed and demonstrated at 2.4 GHz and has a linear and continuously tunable range of 120[degrees] across the 2.4-GHz industrial-scientific-medical band. Index Terms--Active circuits, circulators, CMOS, monolithic microwave integrated circuit (MMIC) phase shifters, multiple-input multiple-output (MIMO) systems.

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-[micro]m CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at 35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and > 32-dB isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point ([IP.sub.1] dB) can be significantly increased to ~ 23 dBm with the use of a high substrate resistance design. In contrast, [IP.sub.1 dB] of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13-/[micro]m CMOS designs can be used for state-of-the-art switches at 26-40 GHz. Index Terms--CMOS switch, Ka-band, millimeter wave, RF switch, single-pole double-throw (SPDT) switch, single-pole single-throw (SPST) switch, substrate networks, 0.13-[micro]m CMOS.

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-[micro]m CMOS technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of +0.1 dBm. Index Terms--CMOS analog circuits, linearization techniques, low-noise amplifier (LNA), mixer design, receiver topology.

Tuned ring oscillators are used to generate multiple phases of a sinusoid for a variety of applications including phased-array transceivers and clock and data recovery circuits. A variable-phase ring oscillator (VPRO) is presented that generates outputs with a controllable phase progression, enabling its use in a compact low-power single-chip phased-array transceiver architecture. The VPRO functionality is shown to be robust with respect to process and layout mismatches. This enables the implementation of integrated phased arrays with acceptable array performance even in the absence of mismatch calibration circuitry, which are essential in other phase-shifterless schemes such as coupled oscillator arrays. A prototype 24-GHz four-channel single-chip phased-array transceiver implemented in a 0.13-[micro]m CMOS process is presented to validate these claims. Index Terms--CMOSFET oscillators, error analysis, oscillators, phased arrays, quadrature amplitude modulation (QAM).

This paper presents a precision current sensor featuring a high voltage, high gain (~ 140dB), and low input offset ( Index Terms--Amplifier, CMOS, common, current, gain, gate, high, offset, sense, voltage.

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-[micro]m CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than [10.sup.12] when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of [2.sup.15]--1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval ([UI.sub.pp]) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 [UI.sub.pp] by applying PRBS data with a pattern length of [2.sup.31]--1. Index Terms--Clock-and-data (CDR) recovery circuits, data communication circuits, full on-chip CDR, monolithic CDRs, OC-192, phase-locked loops (PLLs), SONET.

This paper describes a unique remote laboratory for studying CMOS physical defects that is meant to be used in advanced courses in the scope of microelectronic design and test. Both the measurement equipment and the remote access mechanism were custom developed in the frame of the European Union project REASON. The core of the equipment is an educational chip that contains different manufacturing defects physically implemented into standard digital cells and small logic circuits on the layout level. The chip is supplied with a dedicated plug-and-play measurement box, which provides an interface between the chip and the training software. This measurement kit offers a glimpse into the silicon reality, revealing behavior of the most common defects and their influence on the circuits' operations. Students can choose between approximately 500 different defects, which can be classified into different groups by studying their properties, and find differences or similarities. The remote server-based version of the laboratory is accessible over the Internet, thereby supporting distance learning and e-learning modes of training. A personal version of the training software is also available. Index Terms--Built-in current monitor, distance learning, e-learning, fault modeling, manufacturing defects, remote laboratory, test pattern generation.

In this paper, an implementation of a tunable highly linear floating resistor that can be fully integrated in CMOS technology is presented. The second-order effects of a single MOS transistor operating in the triode operation regime are described, and a common-mode finearization technique is applied to suppress these nonlinearities. This technique is implemented by utilizing a low-power circuit design strategy that exploits the capacitive coupling and the charge storage properties of floating-gate transistors. The resistance of the proposed circuit is tuned by utilizing the Fowler-Nordheim tunneling and hot-electron injection quantum-mechanical phenomena. We demonstrate the use of this resistor in highly linear amplifier. We present experimental data from the chips that were fabricated in a 0.5-[micro]m CMOS process. We show that this resistor exhibits 0.024% total harmonic distortion (THD) for a sine wave with [1-V.sub.pp] amplitude. Also, we show the programmability of the amplifier gain using the proposed tunable resistor. Index Terms--CMOS, floating gate, resistor, tunable.

The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-of- the-art CMOS process technology. Index Terms--Contact, gate, leakage current, test structure.

This paper proposes an accurate four-transistor temperature sensor designed, and developed, for thermal testing and monitoring circuits in deep submicron technologies. A previous three-transistor temperature sensor, which utilizes the temperature characteristic of the threshold voltage, shows highly linear characteristics at a power supply voltage of 1.8 V or more; however, the supply voltage is reduced to 1 V in a 90-nm CMOS process. Since the temperature coefficient of the operating point's current at a 1-V supply voltage is steeper than the coefficient at a 1.8-V supply voltage, the operating point's current at high temperature becomes quite small and the output voltage goes into the subthreshold region or the cutoff region. Therefore, the operating condition of the conventional temperature sensor cannot be satisfied at 1-V supply and this causes degradation of linearity. To improve linearity at a 1-V supply voltage, one transistor is added to the conventional sensor. This additional transistor, which works in the saturation region, changes the temperature coefficient gradient of the operating point's current and moves the operating points at each temperature to appropriate positions within the targeted temperature range. The sensor features an extremely small area of 11.6 X 4.1 [micro] [m.sup.2] and low power consumption of about 25[micro]W. The performance of the sensor is highly linear and the predicted temperature error is merely -1.0 to + 0.8 [degrees]C using a two-point calibration within the range of 50 [degrees]C to 125 [degrees] C. The sensor has been implemented in the ASPLA CMOS 90-nm 1P7M process and has been tested successfully with a supply voltage of 1 V. Index Terms--CMOS, temperature coefficient, temperature sensor, thermal diode, thermal monitoring, two-point calibration.